Infinite looping in NIOS-II Eclipse alt_irq.h

[sirujjan]

Good day gentlemen

I am facing problem related to either the NIOS-II Eclipse processing or DDR2 SDRAM memory interfacing in platform designer.

I am using DE-4 board which have two on-board DDR2 SO-DIMM modules each of 1GB. In my design I require to use both of them. My qsys design is shared here. While testing the memory in Eclipse with its given memory testing template program, one of the module (DDR2_1 in qsys) works perfect and pass all the test. While as the second module DDR2_2 is not functioning properly. It passes 3 tests out of 4 (i.e. data bus, address bus, 8bit/16bits access) but fails in the 4th test that checks every location by saving data, inverting bits and inverting again. Here it starts OK in debug mode, even in this 4th test some of loops it process fine but all of sudden it jumps to the ALT_IRQ.h program file where it stucks in a never ending loop.

My design timer counter size = 64; period 1ms

DDR2_1 & DDR2_2 both have same parameters selection operating at Pll_ref_clk = 50MHz; memory clock = 400MHz; afi_clk = 200MHz.

Memory test template program works for DDR2_1 but DDR2_2 hangs up. There is no issue in memory chip itself as I have tested by exchanging their slots on DE board and also using control panel program which works perfect for both RAMs. May be I am making errors in timings, interfaces etc. for the second DDR.

Can you please check my qsys connections, pipeline and MM-clocking bridges, master-slave connections? 
Thanks in advance

[sirujjan]

Hopefully, I will receive some expert response.

[JingyangTeh]

Hi

Could you share with us both DDR memory test logs so we could take a look.

Regards

Jingyang, Teh

[AdzimZM_Intel]

Hello,

Can you try to separate the PLL reference clock source for both DDR2?

• Maybe you can provide DDR2_1 PLL reference clock source from OSC_50_B3 (PIN_AV22).
• And DDR2_2 PLL reference clock source from OSC_50_B4 (PIN_AV19).

Regards,

Adzim

[JingyangTeh]

Hi sirujjan

Did you tried out the suggestion from Adzim in the previous comment?

The DDR2 module would need separate clocks instead of sharing a single clock.

Regards

Jingyang, Teh