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Interfacing SRAM to NIOS

Altera_Forum
Honored Contributor II
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Hi,  

 

I am using a Cypress CY7C09289V-12A SRAM on my prototype FPGA board. I wish to use this for my NIOS II code.  

I have added a SRAM (IDT71V416S) and a tristate bridge to my qsys and have connected them accordingly.  

I had to change the address and data widths to match my SRAM.  

Then i have assigned the appropriate pins in my Quartus. For this IC i have enabled ADS_n signal and disabled CNTRST_n signal.  

I have given a 40 MHz clk to the IC 

 

I am getting "Downloading ELF process failed" when i try to download the NIOS II code from Eclipse.  

 

Kindly let know what could i be doing wrong ? 

 

regds 

Santhosh
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Altera_Forum
Honored Contributor II
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The first step would be to add some on-chip memory to your Nios system and put there a memory test software (there is one in the templates list). Then use that software to test the SRAM

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Altera_Forum
Honored Contributor II
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This board which am using is not an altera board. Its a prototype board for our purpose.  

Moreover which templates are u telling about ?  

This is urgent, if someone could help, it would be helpful 

 

regds 

santhosh
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Altera_Forum
Honored Contributor II
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In Eclipse, when you create a new software project, there is a memory test template.

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