Is it possible to modify Calibration Logic when using External Memory IP on Agilex FPGA?

[kwangkyu]

hello. We are now using Agilex FPGA. We are using External Memory IP, and calibration is performed using Calibration IP. I want to mask some DUTs during calibration through NIOS. Is it possible?

[AdzimZM_Intel]

Hello kwangkyu,

Thank you for submitting your question in Intel Community.

I am Adzim and I will assist you on this thread.

The calibration process is in the harden IP that user may not interfere the process.

User may not be able to modify the calibration logic because it's not expose to user logic.

Regards,

Adzim

[AdzimZM_Intel]

Hi kwangkyu,

Is there any update on this case?

Thanks,

Adzim

[AdzimZM_Intel]

As we do not receive any response from you on the previous reply that we have provided, I now transition this thread to community support. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.