I’m working with a MAX 10 device (DECA development board) to transfer data from a FIFO to the DDR3. I’m using a Scatter Gather DMA and a EMIF DDR3 controller to transfer the data. The DMA works with a 150 MHz clock, as the Avalon MM bus of the EMIF interface. The data are correctly transferred, but it seems that are not transferred at the maximum throughput. As you can see from the image, the “avl_ready” signal from the DDR3 is always high, while the “m_write_waitrequest” that goes to the DMA is high for 4 clock cycles and low only for one for each data actually written in the DDR3. I think that the Platform Designer puts some logic between the DMA and the EMIF, because I think that the m_write_waitrequest signal should be the opposite of the avl_ready signal and transfer one data per clock cycle when avl_ready is low.
Why it happens?
To isolate your issue to find the bottleneck, you can start with small design first then only slowly add more design block into it.
For instance :
- Create DDR3 only design and test the performance
- Then upgrade to DDR3 + DMA design (without using QSYS)
- Then upgrade to DDR3 + DMA design (with using QSYS)