NIOS II PIO Data read problem

Altera_Forum · ‎04-05-2012

Hi All.

I have some problems with data processing, based on NIOS core. My FPGA project includes external interface, strobe line (NIOS Internal interrupt or just Flag), 8 bit data input port and FIFOed UART (as stdout).

I try to read PIO data from Port, but i see that they are wrong (I have ana another external UART for Debug, included before the NIOS Port).

I have no Idea, what is wrong.

Please, tell me...

Source code:

while(1)

{

do

{

edge = IORD_ALTERA_AVALON_PIO_DATA(STROBE_BASE);

IOWR_ALTERA_AVALON_PIO_EDGE_CAP(STROBE_BASE, 0x0);

}

while(edge & 1);

data = IORD_ALTERA_AVALON_PIO_DATA(DATA_BASE);

printf("0x%02X ",data);

IOWR_ALTERA_AVALON_PIO_EDGE_CAP(DATA_BASE, 0x0);

do

{

edge = IORD_ALTERA_AVALON_PIO_DATA(STROBE_BASE);

IOWR_ALTERA_AVALON_PIO_EDGE_CAP(STROBE_BASE, 0x0);

}

while((edge & 1) == 0);

}

Thank you...

Altera_Forum · ‎04-05-2012

First of all you must write ones, not zero, into edge capture register to reset status:

IOWR_ALTERA_AVALON_PIO_EDGE_CAP(STROBE_BASE, 1)

Anyway this seems to be irrelevant, unless you are using edge capture in another part of the code.

I guess your problem is that you can't get the correct pio status in 'data', isn't it?

This can be simply due to bad timing relative to strobe signal.

Altera_Forum · ‎04-05-2012

Yes it is. I can not get a correct data from PIO port inside NIOS core. I have an idea about wrong external timing signal for STROBE input. In addition, it seems to me, that i can sometimes read data at the same time that as they are changes. Can i use triggered buffer for this data?

Altera_Forum · ‎04-10-2012

I don't know the timing of your signals, but if you are really getting data when it is changing, I think you should read it after the second while loop or maybe read after a short delay.

If you can change the 'hardware' part (I mean fpga design) besides Nios software, I suggest you add a bit of glue logic in order to latch your pio data when the strobe signal becomes active. In other words you

make the same as those while loops but in a more efficient and stable way, at the expense of using a few more fpga resources.