NIOS II SPI Slave with FIFO

[SAN]

Hi,

I would like to receive N bytes of data using SPI(3 Wire Serial) IP in Qsys.

All N bytes are transferred by the master during one chipset toggle.

I implemented the RX interrupt, but I could see only the last byte.

(Previously received data is overwritten)

So, I think I need a FIFO that can store the received data.

But ​I do not know what to do.

Can somebody give me an advice? 

Thank You.

[Vicky1]

Hi,

Try to set the bits in control Register & then check status of the status Register.

Best Regards

Vikas Jathar 

(This message was posted on behalf of Intel Corporation)