07-20-2015 08:21 PM
I have code running on the Stratix V + NIOS II with IMEM and PCIe IP.At some point the NIOS II hangs and I can't break in with the dubugger. Is this symptomatic of the NIOS II being stuck in a Load or Store operation ? I would like to use a non-buffered , non-interrupt driven stdio driver so that any printf is synchronized to where the program flow is ... So.. how to break in with the debugger and how to run non-buffered stdio. I am using the JTAG UART ... so it may be more difficult than a straight UART. I can use the LED's or the LCD on the Stratix V card as a "checkpoint" display but would rather leave the print statements or really be able to break in with the debugger. background : The same application works with Cyclone ... card ... ... The host sets a linked list of descriptors in in host, RC memory, informs the NIOS II via a mailbox IMEM where the head of the descriptor list is and the Host and the NIOS II work down the list and at a certain point the NIOS II hangs ....
07-20-2015 11:12 PM
I think you're seeking alt_log_printf()https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/nios2/edh_ed51003.pdf When things go off the deep end, the best tool unique to this environment that I have found is the SignalTap NIOS plugin, which doesn't get mentioned very frequently: https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/an/an446.pdf And along the similar lines as writing to your LED's, you can also do things like have an assortment of PIO instances that you don't tie to anything except SignalTap or a Sources/Probes instance. For example, one PIO for "module" and one PIO for "line number" and riddle your code with TRACE() macros that write to those PIO's; hookup SignalTap and watch the writes to those PIO leading up to your crash. As far as why you are unable to break into your program, I've experienced the same but I don't think it is necessarily a load/store being stuck. Anyway - lots of things you can try, without feeling dependent on unbuffered UART's and LED's.
07-20-2015 11:30 PM
Thanks Ted....We have narrowed one fail on Stratix V PCIe at Gen3 X 4 to be some failure of a byte write, int writes operate fine but for some reason the byte write by NIOS II outbound to host memory turns into a 4 DWORD PCIe operation which I am not even sure is legal ... This is seen at both Gen3 X 4 and Gen1 X 4. I can either try to simulate it with a bus master replacing the NIOS II data master or as you indicate employ Signal Tap to see what transaction NIOS II sent to the PCIe TXS slave. Thanks Bob. Attached is an analyzer trace of what was supposed to be a byte write .. but I think the non contiguous byte enables is not legal.
07-21-2015 04:26 PM