Re: NIOS2 & mSGDMA (Ethernet example)

Altera_Forum · ‎07-10-2018

Hello,

I am trying to build the Ethernet hardware system for the NIOS2 "Simplified TCP server" example, for the Arria 10 Gx Developpemnt kit.

I am having two problems with the mSGDMA IP. I upgraded the original design from SGDMA to mSGDMA because the BSP failed and I read somewhere on these forums that with recent (>16, I am using 17.1) quartus, we should be using mSGDMA. And it seems correct because my BSP almost builds correctly now.

in the platform designer, I can't seem to figure out how to connect an "On Chip Memory" storing the DMA descriptors (they will come from software) to mSGDMA. I have two mSGDMA devices, one for RX one for TX, connected to TSE. Can someone explain precisely how to connect the "descriptor_slave" Avalon Memory Mapped interfaces of those DMA devices to a memory storage?

when I try to build the BSP from this design it almost succeeds. When I was using the example design it failed at the first step of the "altera_iniche" compilation. Now it goes a little further by I am getting errors like:


      alt_sys_init.c: 107:51: error: 'eth_subsystem_msgdma_rx' undeclared (first use in this function) ...
      in definition of macro 'ALTERA_MSGDMA_INIT'
      
      alt_sys_init.c: 107:51: error: 'eth_subsystem_msgdma_tx' undeclared (first use in this function) ...
      in definition of macro 'ALTERA_MSGDMA_INIT'

eth_subsystem_msgdma_tx/rx are the name of the mSGDMA devices, they are both included in a subsystem in SOPC. It's like the SOPC description is corrupted somehow but it does specify I am using mSGDMA devices and their names are correct too.

any input would be highly aprreciated, thanks

Altera_Forum · ‎07-13-2018

Hi there,

The descriptor_slave should connect to the .data and .instruction Master of your NIOS processor. To my understanding, this is where the descriptors are written to when you call construct_standard_mm_to_mm_descriptor(). The Data_read_master connects to your memory where the source data resides, and the write data master should connect to the memory where you want the source data to be written.

The error you are having seems to be caused by the BSP having the wrong settings. In my case, it didn't recognize a timestamp function, eventhough it sees the required header file in the project tree. I still managed to generate the BSP, just not the project containing my DMA controller code.

Hope this helps.

Altera_Forum · ‎07-17-2018

lostdestiny,

thank you for your help

--- Quote Start ---

The descriptor_slave should connect to the .data and .instruction Master of your NIOS processor. To my understanding, this is where the descriptors are written to when you call construct_standard_mm_to_mm_descriptor(). The Data_read_master connects to your memory where the source data resides, and the write data master should connect to the memory where you want the source data to be written.

--- Quote End ---

my system consists of a NIOS2, on OnChipMemory (OCM) which acts as the RAM pool for the NIOS system, I would like the DMA controller to send data to this memory, so indeed I connected the master interface of the DMA controller to the Pipeline bridge. The descriptor slave interface of the DMA controller was connected to the Master interface of the CPU bridge, as I thought it would directly receive instructions from the CPU.

I did not connect the CPU/instruction master interface to the DMA controller (as you mentionned it), I tried to do so, but I keep getting "CPU/instruction master is read only while the CPU/instruction master is write only" which I don't understand, it's not connected to itself, I already have devices on the instruction master line, I am just trying to add a new one.

Here's what I tried:

DMA-Controller
DMA-Controller
DMA-Controller
cant connect descriptor slave to instruction master because of previous error
cant connect descriptor slave to a master interface without connecting

Here's my code:


alt_u32 dma_buf; // work buffer / OCM??
alt_msgdma_dev *dma_dev;
alt_msgdma_standard_descriptor rx_descriptor;
// tried with & without it --> alt_msgdma_standard_descriptor rx_descriptor ___attibute__ ((section(".onchip_memory"));
// copied from available example, I doubt we need this though because
// the API sets the destination address when we build the descriptor right?
main(){
  
  dma_dev = alt_msgdma_open("/dev/msgdma_csr");
  alt_msgdma_construct_standard_st_to_mm_descriptor(
     dma_dev,
     &rx_descriptor,
     (alt_u32*)dma_buf,
     256*sizeof(int),
     0
   );
   dma_status();
   alt_msgdma_standard_descriptor_async_transfer(dma_dev, &rx_descriptor);
   dma_status();
}

my dma_status() routine checks the CSR status reg, the first one (right after build_descriptor()) says "RESET state + descriptor buffer EMPTY".

The second one, right after _async_transfer() says "descriptor buffer EMPTY", which lets me think there is some activity but I am not able to control my DMA descriptors properly.

I haven't tried direct register access yet, like setting the GO bit & manually controlling the descriptors, I think I should be able to get the API to work.

Is an OCM dedicated to DMA descriptors mandatory?

Is CPU/Instruction master connection mandatory?

How can I connect an OCM/FIFO to store DMA descriptors to the DMA controller with connecting the [mm_write] interface??

Altera_Forum · ‎07-24-2018

thank you for your help,

I succeeded in using the mSGDMA devices, in a loopback demo. My understanding is the new TSE driver suite that comes in a BSP requires mSGDMA devices, no longer SGDMA.

So now I got something that should be fairly close to what I want. I have a NIOS2 + TSE + two mSGDMA devices and a dedicated OCM for DMA descriptors.

The point is I am trying to create a basic design to use the TCP demo application, now I can get the app to start but it is stuck at "Auto negotiation passed" and simply hangs there.

The two NicheStack tasks (tick & netmain) are both created. The MDIO interface seems to be working and the drivers seems to do the job. But then it requests a hardware reset, reinitiates a negotiation & just freezes.

Any ideas what I might be doing wrong?

I noticed on an online tutorial that what comes next is related to DMA devices, could that possibly be related to my OCM/DMA whatever SOC I did wrong?

https://alteraforum.com/forum/attachment.php?attachmentid=15825&stc=1

AKb · ‎08-14-2020

Hi,

I am trying to implement triple speed ethernet in nios processor using modular scatter gather dma (msgdma) controller. I have build the qsys. For memory i have used ram. I have called 2 msgdma one for receiving in streaming to memory mode and one for transmitting in memory to streaming mode. I have done the interconnections in qsys platform and generated the HDL successfully. The sopcinfo file is also generated. Using this sopcinfo file i tried to generate the bsp. The bsp generates but when i try to build the bsp project in eclipse the build fails. It says that " fatal error. altera_msgdma.h. No such file exists."

I am using Quartus 18.1. I cannot downgrade to lower version as i have progressed a lot in 18.1 and now cannot migrate to a lower version because of dependency issues.

Actually this file is missing in alt_avalon_tse.h. The altera_msgdma.h exists in the installation folder of quartus 18.1 in c drive. But some how when i try to build the bsp it doesn't pick that file and throws the above mentioned error. I have tried to manually move altera_msgdma.h and altera_msgdma.c file into the incude and source file of the driver folder of the project file. After doing this the bsp builds, but the actual project build fails.

Kindly guide

Regards

Av

AKb · ‎08-16-2020

Hi,

I am trying to implement triple speed ethernet in nios processor using modular scatter gather dma (msgdma) controller. I have build the qsys. For memory i have used ram. I have called 2 msgdma one for receiving in streaming to memory mode and one for transmitting in memory to streaming mode. I have done the interconnections in qsys platform and generated the HDL successfully. The sopcinfo file is also generated. Using this sopcinfo file i tried to generate the bsp. The bsp generates but when i try to build the bsp project in eclipse the build fails. It says that " fatal error. altera_msgdma.h. No such file exists."

I am using Quartus 18.1. I cannot downgrade to lower version as i have progressed a lot in 18.1 and now cannot migrate to a lower version because of dependency issues.

Actually this file is missing in alt_avalon_tse.h. The altera_msgdma.h exists in the installation folder of quartus 18.1 in c drive. But some how when i try to build the bsp it doesn't pick that file and throws the above mentioned error. I have tried to manually move altera_msgdma.h and altera_msgdma.c file into the incude and source file of the driver folder of the project file. After doing this the bsp builds, but the actual project build fails.

Kindly guide

Regards

Av

AKb · ‎08-21-2020

Hi,

I am trying to implement triple speed ethernet in Cyclone 10 FPGA. I have integrated triple speed ethernet core in platform designer in qsys. If i pump data and do loop back in system side of MAC, its working fine. I am able to monitor Start of packet, data valid, data, End of packet properly in signal tap. Now my aim is that i try to capture the streaming data in system side of MAC directly in Nios side memory. For this i am using Modular Scatter gather DMA. For receive data i am using one MSGDMA in streaming to memory mode and one for transmit data i am using one MSGDMA in memory to streaming mode. I try to capture data in descriptor memory in onchip ram. But i am not getting any data.

I have doubt about my connections of MSGDMA in Qsys.There are no any specific examples detailing how to use MSGDMA with TSE. Some people have done it with SGDMA . I am using quartus 18.1. So how to go about it. How to capture data in onchip RAM.

Kindly guide

Av

MichaelV · ‎01-08-2021

Hello,

did you ever resolved the error regarding undeclared variable names?