Neek - Uart

Altera_Forum · ‎04-28-2010

im just a newbie in FPGA programming

just want to ask how to add a UART (rs232) into the hardware design.

I already tried to add it on SOPC builder and generate

and recompile it on quartus.

unfortunately its not working.

i am using a simple code transmitting a character (NEEK is connected on my PC using hyperterminal)

i know my code is working because i tried it on a sample design with a built in UART.

I hope you can help me and tell me what did i miss or something wrong on my process.

#ifdef AVALON_UART# else
// set line control reg to allow writing to baud divisor
IOWR_8DIRECT (UART_BASE, 3, 0x80);
// baud divisor = (clk) div (baud) div (16)
// 50M/115200/16 = 27.127 = 0x001B
// 30M/115200/16 = 16.276 = 0x0010
// 30M/9300/16 = 195
IOWR_8DIRECT (UART_BASE, 1, 0x00); // baud div hi
IOWR_8DIRECT (UART_BASE, 0, 16); // baud div lo
// set line control reg for 8 n
IOWR_8DIRECT (UART_BASE, 3, 0x03);# endif
{
 int x=0;
 char msg = 'A';
 FILE* fp;
 fp = fopen ("/dev/uart", "w");
 for(;;)
 {
 printf("waiting for input: \n");
 scanf("%d",&x);
  if (fp == NULL)
  {
  printf("cant access file");
  }
  if (x==1 & fp!=NULL)
  {
   printf("character sent\n");
   fprintf(fp, "msg");
   fclose (fp);
  }
  x=0;
 }
 return 0;
}

the software successfully compiled so i think there is no problem on that part (i've checked already the file path for uart and UART BASE name on system.h)

Altera_Forum · ‎04-30-2010

Did you connect the uart ports from the sopc component to the fpga pins in your design?

Altera_Forum · ‎05-01-2010

is it the assignment on pin planner?

i tried to assign pins on pin planner by assigning HC_UART_RXD to E18 and HC_UART_TXD to H17.

am i doing it right? can you please give me the steps in adding components, especially the UART in hardware design in quartus/SOPC.

thank you for the response.

Altera_Forum · ‎05-03-2010

You need to do two things:[list][*]create the pins in the pin planner, as you did

[*]connect those pins to the SOPC component in your top level design file[/list]

Altera_Forum · ‎05-03-2010

--- Quote Start ---

connect those pins to the SOPC component in your top level design file

--- Quote End ---

i put this codes on the verilog top level design:

(i declare input and output pins for cyclone III)

output HC_UART_TXD;

input HC_UART_RXD;

is this how you connect SOPC component? because when i try to locate the pin from the pin planner, it shows me this part on the design file, so i assumed that i already connected the SOPC component.

Altera_Forum · ‎05-04-2010

Yes, you declared the pins in the top level design file, and assigned them in the pin planner.

Now you actually need to connect those to the SOPC component. Scroll further down in the verilog file and you should find the SOPC instantiation.

Altera_Forum · ‎05-04-2010

yes, i found the sopc instance.

what i did there, i put some code like this:

.rxd_to_the_uart (HC_UART_RXD),

.txd_from_the_uart (HC_UART_TXD),

i just copy it on other design with built in uart, but i check the block diagram for the pin name. am i doing right? with this, i think im still missing some steps.

Altera_Forum · ‎05-05-2010

No I think you have everything now.

Altera_Forum · ‎05-06-2010

Thanks for the help sir Daixiwen, now i know that i had already added the UART device on my design.

I think i need to check for other reasons. Thanks to you again.

Altera_Forum · ‎05-10-2010

If you have a scope you can check if any signal is going in and out of the UART. Check also that both ends have the same configuration (baud rate, start/stop bits, parity...)

Altera_Forum · ‎05-11-2010

thanks to you sir Daixiwen

I already got the problem, there are two SOF, the sample (which is not updating) and the limited time SOF (which is updating as i compiled it on quartus).

I did not notice that there are two SOFs, because I used to configure SOF on nios command shell and the sample SOF was the one loading on my FPGA.

But still, I want to thank you for helping me to figure out the problem. I thought it was the hardware design.

Altera_Forum · ‎05-12-2010

That's a tricky one... I wonder if it is really necessary for Quartus to change the file name like that when using the Opencore evaluation. There is certainly better ways of telling it to the user!