Nios 2 processor cores

[Altera_Forum]

We've just had our Nios 2 DKs installed. Since we are targeting a standard core to use in a Cyclone device, the software engineer asked if there were a way to not use the instruction bus cache at all without having to go to an economy core. From the SOPC builder, it didn't seem like this was possible to disable. Thanks.

[Altera_Forum]

I bet it's a hidden choice. I'll see if I can find out for you.

[Altera_Forum]

Unfortunately this currently isn't a hidden feature. 

I expect it will be coming in a future release in a few weeks or in the worst case 6 months (depends which release it makes it into).

[Altera_Forum]

Are there any other changes that are scheduelled? Like being able to use the hardware divider in the 's' core for example (I tried modifying the settings file to enable the hardware divide for that core and it didn't seem to work (unless I did something wrong)). 

 Also James, besides the ability to disable the hardware multiplier circuit in the settings file (thanks for pointing that out with the 's' core fmax problems I was having), are there any other things that can be changed to get around the settings of the 3 fixed systems?

[Altera_Forum]

I refactored the perl code used to generate the Nios II cores to allow more sharing 

and more options. That will show up in Nios II 1.1 near the end of the year. I'm not sure which of these will make it into that release because adding options dramatically increases our testing burden. Here's some possible options:  - Static or dynamic branch prediction (Nios II/s currenly uses static, Nios II/f currently uses dynamic)  - Optional instruction cache for Nios II/s and Nios II/f  - Optional data cache for Nios II/f  - Hardware divide support for Nios II/s (your specific request)  Besides divide for Nios II/s, do any of these look interesting to you?

[Altera_Forum]

James, thanks for the possible options. The one we would be interested is the option for the instruction cache for the II/s core without having to use the smaller II/e core.

[Altera_Forum]

Those changes sound pretty good to me http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif

[Altera_Forum]

The ability to turn off either cache would be good for people like me who use the custom bus interface a lot. I end up setting my cache to the bare minimum since I end up bypassing it almost all the time. 

 As for instruction cache, I use to avoid it at all cost due to the fmax hit I&#39;d take with NIOS I, now it seems fine to have it around (but being able to omit it would be nice since I have no clue if it&#39;s helping or hindering my design).