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Hello friends,
My software on nios SBT put high on PIO_STRT_OUT pin IOWR_ALTERA_AVALON_PIO_DATA(PIO_STRT_OUT_BASE,HIGH), and it reflect (STRT) on output also (attached printscreen), this start out trigger a 8 bit parallel to serial (P2S) converter external to nios processor (attached printscreen), and then this P2S generate a load pulse (LD) which feedback to processor, which tells processor that give a one byte of data (DATA[7..0]) stored in an array, Problem: output DATA[7..0] first word 164 is available for jut 5 and ½ clock period not for 8 clock period like rest of the data is available for 8 clock as load pulse arrive every 8th clock pulse. Regards kaushalLink Copied
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