PIO cores

[Altera_Forum]

Hi people, 

A simple doubt:  I'm trying to develop a multi-processor system in which the processors exchange informations (data) though PIO cores. In the Quartus projects I've switched the outputs of the SOPC component directly in the correspondent inputs in the same component (SOPC instance) through buses (Orthogonal Bus Tool). Can I do that or the PIO Cores must be necessarily switched to output/input pins? Am I in risk of damage my Nios FPGA making connections between processors in this way?  Thanks. mendonca

[Altera_Forum]

I don't think so... we also do a similar thing to implement multiprocessor interrupts... 

 Btw, why are you using PIOs instead of shared memory?  Paolo

[Altera_Forum]

Paolo, 

I'm using PIO once my application demands high degree of parallelism. When I use a shared memory the processors "suffer" with the conflict in access it. The use of extern memories, as DDR SDRAM, to store stack, heap, data and instructions also presents a obstacle to my goals, my implementation is big enough so that it doesn't fit totally on-chip. I'm trying to minimize this problem.  But thank you too much, Paolo. If the use of PIOs cores "among" processors didn't damage your board I think I'm safe to try my experiments. If you (or somebody else) have some suggestions about resources offered by Nios which can help me to improve the parallelism among my processors, they will be welcome.  Regards, mendonca.

[Altera_Forum]

--- Quote Start ---  originally posted by mendonca@May 12 2006, 03:35 PM paolo, i&#39;m using pio once my application demands high degree of parallelism. when i use a shared memory the processors "suffer" with the conflict in access it. the use of extern memories, as ddr sdram, to store stack, heap, data and instructions also presents a obstacle to my goals, my implementation is big enough so that it doesn&#39;t fit totally on-chip. i&#39;m trying to minimize this problem.  but thank you too much, paolo. if the use of pios cores "among" processors didn&#39;t damage your board i think i&#39;m safe to try my experiments. if you (or somebody else) have some suggestions about resources offered by nios which can help me to improve the parallelism among my processors, they will be welcome.  regards, mendonca. <div align='right'><{post_snapback}> (index.php?act=findpost&pid=15345)  --- quote end ---    --- Quote End ---   mendonca, to make 2 (or more) processors exchange informations with PIO, the PIO core should be connect to the DATA MASTERS of each processor,and a Mutex should be added into your multiprocessor system.Besides,you should request a lock of the mutex core in your software codes before accessing the shared resource(PIO core).  i have completed a multiprocessor system which an on-ship memory and a LED PIO is shared in for test.The documents in the Nios directory help me a lot. This document is helpful to you too,i think. http://www.altera.com/literature/tt/tt_nio...or_tutorial.pdf (http://www.altera.com/literature/tt/tt_nios2_multiprocessor_tutorial.pdf)  sorry for my english expression.  good luck, vincent

[Altera_Forum]

--- Quote Start ---  originally posted by mendonca@May 12 2006, 03:35 PM paolo, i&#39;m using pio once my application demands high degree of parallelism. when i use a shared memory the processors "suffer" with the conflict in access it. the use of extern memories, as ddr sdram, to store stack, heap, data and instructions also presents a obstacle to my goals, my implementation is big enough so that it doesn&#39;t fit totally on-chip. i&#39;m trying to minimize this problem.  but thank you too much, paolo. if the use of pios cores "among" processors didn&#39;t damage your board i think i&#39;m safe to try my experiments. if you (or somebody else) have some suggestions about resources offered by nios which can help me to improve the parallelism among my processors, they will be welcome.  regards, mendonca. <div align='right'><{post_snapback}> (index.php?act=findpost&pid=15345)  --- quote end ---    --- Quote End ---   mendonca, to make 2 (or more) processors exchange informations with PIO, the PIO core should be connect to the DATA MASTERS of each processor,and a Mutex should be added into your multiprocessor system.besides,you should request a lock of the mutex core in your software codes before accessing the shared resource(PIO core).  i have completed a multiprocessor system which an on-ship memory and a LED PIO is shared in for test.The documents in the Nios directory help me a lot. This document is helpful to you too,i think. http://www.altera.com/literature/tt/tt_nio...or_tutorial.pdf (http://www.altera.com/literature/tt/tt_nios2_multiprocessor_tutorial.pdf)  sorry for my english expression.  good luck, vincent

[Altera_Forum]

--- Quote Start ---  originally posted by mendonca@May 12 2006, 10:35 PM i&#39;m using pio once my application demands high degree of parallelism. when i use a shared memory the processors "suffer" with the conflict in access it. the use of extern memories, as ddr sdram, to store stack, heap, data and instructions also presents a obstacle to my goals, my implementation is big enough so that it doesn&#39;t fit totally on-chip. i&#39;m trying to minimize this problem. <div align='right'><{post_snapback}> (index.php?act=findpost&pid=15345)  --- quote end ---    --- Quote End ---    Sorry bu I did not understand... I think passing data through PIO will be much more heavyweight than using a -little- shared memory... but if you are happy like that :-)    --- Quote Start ---  originally posted by mendonca@May 12 2006, 10:35 PM but thank you too much, paolo. if the use of pios cores "among" processors didn&#39;t damage your board i think i&#39;m safe to try my experiments. if you (or somebody else) have some suggestions about resources offered by nios which can help me to improve the parallelism among my processors, they will be welcome. <div align='right'><{post_snapback}> (index.php?act=findpost&pid=15345)  --- quote end ---    --- Quote End ---    As long as I know, there is the Multiprocessor tutorial from Altera available on the Altera web site, as well as a 2CPU example for the 1s40 evaluation board at the evidence literature page for nios ii (http://www.evidence.eu.com/nios2)  bye  Paolo

[Altera_Forum]

Sorry for my confused reply, Paolo. 

Actually I&#39;m not sure yet about the advantages to use PIO cores instead a shared memory. My problem with the shared memoy is the delay that processes have waiting for the release of mutexç with pio cores i hope not to have this problem.

[Altera_Forum]

--- Quote Start ---  originally posted by mendonca@May 15 2006, 07:50 PM sorry for my confused reply, paolo. actually i&#39;m not sure yet about the advantages to use pio cores instead a shared memory. my problem with the shared memoy is the delay that processes have waiting for the release of mutexç with pio cores i hope not to have this problem. <div align='right'><{post_snapback}> (index.php?act=findpost&pid=15387)  --- quote end ---    --- Quote End ---     Everything depends on how much data you need to share, and on how the communication works. Implementing a message passing mechanism that does not waste all the time in synchronization is possible!  With PIO, you&#39;ll get probably one word at a time, bu you&#39;ll need to handle the handshaking, and that will require probably more time than doing it with shared memory + mutex.  In any case, the problem of conflicts between different accesses to the same memory as you cited before will remain.  How much data do you need to move from one CPU to the other?  Take also a look at the FIFO example on the Evidence literature page (see one of the posts below in this page), you can adapt it to have a more coarse grained message passing.  bye  Paolo

[Altera_Forum]

Hi, your name sounds italian. 

I&#39;m from Italy too. Is it possible mantain contact out from this forum too?I&#39;d like to show you my problems using an FPGA Cyclone II. Talking in italian would faster and clearer. Many thanks. Paolo T.