Problems interfacing external SRAM

Altera_Forum · ‎07-12-2004

Hi,

I am having problems with configuring tri-state Avalon bus for accessing external SRAM modules.

I am using 3 is62wv51216bll-70ti (http://www.issi.com/pdf/62wv51216all.pdf) chips.

Anybody used similar chips and wants to share design experiences?

I tried registered Avalon bus and not registered. I clock my Signal Tap with 18MHz cristal and put CPU clock after dividing it by 4. My SRAM is 70ns so it is fast enough for 54*4 cpu clock - I did not set any wait-states.

I am concerned with what I saw with Signal Tap:

I do not see any difference in write transaction cycles between registered and not-registered.

I see two 16-bits bus accesses for one 32-bit integer write. This is ok, but chipselects and write_n signals do not change for two transactions duration. Looks like from the point of view of SRAM, my chipselects and write_n are active when the address changes from x801970 to x801872 and when data changes from x5555 to xAAAA. Suprisingly, subsequent SRAM reads show chipselect and read_n signals change between each 16-bit words being read from the SRAM module. Also, the data being read match the data written previously.

I see some difference on read cycles between registered and not registered bus. Subsequent reads on registered bus are spread further away from each other. In both cases chipselects and with read_n signals.

I am confused... I was expecting the memory write to act on the edge of the write_n signal. Is my signal_tap resulution 4x faster than a cpu clock still to bad to see this bus acting correctly? Or I am missing something important here...

p.s. here is a piece of code I am running for test:

main()

....

int wait;

volatile int * pointer = (int*)0x801970;

*pointer = 0x5555aaaa;

*(pointer+1) = 0xaaaa5555;

wait = *pointer;

wait = *(pointer+1);

....