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Q16.0 QSYS altera_avalon_new_sdram_controller Error Invalid access time t_ac

Altera_Forum
Honored Contributor II
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I have a problem with Q16.0 QSYS SDRAM Controller about : 

Error: sdram0: Invalid access time t_ac (must be < 3.0 ns).  

 

I have searched google about this, there is result not even remotely close. 

In the datasheet Access time from CLK(tAC) is 5.4 ns(max) at CL=3. But the rule check said this value must be less than 3.0 ns. 

And the preset settings are also blocked by this rule. The correct rule should be (must be >3.0 ns) I think. 

 

http://www.alteraforum.com/forum/attachment.php?attachmentid=12507&stc=1 http://www.alteraforum.com/forum/attachment.php?attachmentid=12508&stc=1
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Altera_Forum
Honored Contributor II
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Problem solved, my bad, the Clock Source meant to be 100Mhz but accidentally be set to 1Ghz.

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