I’m modifying an existing Cyclone V Qsys design which is clocked from the HPS H2F user clock at 100 MHz . I need to add an Avalon Bus slave core to this system which requires a 50 MHz interface. It appears this will need it’s own 50 MHz clock reset, clock and Avalon MM bridge to interface to this my slave core. Is this correct or is there a better way to connect this?Thank you for your attention
QSys will automatically take care of synchronizing if the master and the slave are not connected to the same clock. If you need better performance, you can add an Avalon MM clock crossing bridge between the master and the slave.For the reset signal, it depends on how it is defined on the component. If it expects a synchronous released reset then you need to synchronize it with the 50 MHz clock first, for example with a reset bridge IP.