Qsys interconnect

[ASubr1]

I have a Nios II processor system with my own Qsys component which to monitor data memory access. The component has one slave (s1) (Nios data master is connected here) and one master (m1) (slave port of data memory connected here). So inside my component I just pass slave signals to master signals like shown below so that processor can access data memory as normal. (My program is running correctly)

               -- Pass the requests from CPU on to the memory

               avm_m1_address                               <= avs_s1_address;

               avs_s1_readdata                                 <= avm_m1_readdata;

               avm_m1_read                                      <= avs_s1_read;

               avm_m1_writedata                              <= avs_s1_writedata;

               avm_m1_write                                      <= avs_s1_write;

               avs_s1_waitrequest_n                       <= avm_m1_waitrequest_n;

               avm_m1_burstbegin                           <= avs_s1_burstbegin;

               avm_m1_byteenable                          <= avs_s1_byteenable;

               avs_s1_rdata_valid                              <= avm_m1_rdata_valid;

               avm_m1_burstcount                           <= avs_s1_burstcount;

And also inside my component I am counting number of data memory accesses made by the processor. But this counting seems like wrong. I am using this condition to count in every clock cycle: (clock is same for all)

rising_edge(clk) then

if (avs_s1_read = '1' or avs_s1_write = '1') and avm_m1_waitrequest_n = '1' then

Is this correct way to identify ONLY data memory access?

Processor data master is also connected to other slave as well (slave of system id, timer, jtag uart, instruction memory). How Qsys identifies the correct slave port? Using Destination_ID? Is it accessible? or invisible?

Next thing Qsys uses byte address. So we can’t restrict without knowing base address.

Thanks

[Ahmed_H_Intel1]

Hi,

Did you check the interrupt configuration (please share with me these configurations) or use Vectored Interrupt controller VIC instead to see if the same issue exists?

Thanks

[ASubr1]

Hi,

With the EIC using VIC, still we get that unknown accesses but 9 comes to 7. 

Thanks

[Ahmed_H_Intel1]

Can you share with us which errors been solved and which not?