Your SDRAM width should not affect anything software related. When setup properly, the width of the actual SDRAM device should be transparent to the processor. Avalon will simply perform two 16-bit transactions in the background to form a 32-bit word. It should appear the same as any memory to the processor.
Have you stress-tested the interface to your SDRAM? If there is an SDRAM timing problem, it could manifest itself as an intermittent software failure. You may want to check the phase alignment of the SDRAM clock with respect to the data, address and control lines on the board to make sure it's within spec of the SDRAM device. In the example designs that ship with the Nios Development Boards, a PLL is used to phase-align the SDRAM clock. Your board may also require this alignment, although the amount of shift required may likely be different than that which is needed for the Nios Dev Boards.
