Serial Flash Controller II - erase / program issue

[guenniause]

On a customer board (Quartus Prime 18.1 / Cyclone 10 LP / W25Q64) I use the Serial Flash Controller II to access the serial flash W25Q64.

Programming of the flash with JIC-file/Quartus-programmer and booting works fine. However, programming serial flash with Serial Flash Controller II / NIOS does not work reliable. The controller is accessed via the API in the source-file altera_epcq_controller2.c.

Sine it does not work reliably, I monitored the signals to the serial flash. I noticed that after erase or programming actions the busy signal of the flash was not evaluated.

For this purpose I found the function alt_epcq_pll_for_write_in_progress in source file altera_epcq_controller2.c. So I implemented this function in erase_block and write_block (altera_epcq_controller2.c).

After this change erase and programming works reliably.

Is this a known issue and is there a patch available?

[JohnT_Intel]

Hi,

I would not recommend you to use Serial Flash Controller II to access W25Q64 flash as it is not validated to work on the flash. I would recommend you to use Generic Serial Flash Interface IP https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-gen-sfi.pdf.

[guenniause]

Hi,

for Generic Serial Flash Interface IP I found no API, but I found a refenece design with software to access the contoller.

I guess this could the basis to develop an API for our flash.

I use boot_loader_cfi.srec to load and execute application in RAM. Does this code works with Generic Serial Flash Interface IP too?

Thanks,

Guenter

[JohnT_Intel]

Hi,

It should be able to work.

[guenniause]

Hi,

it is basically possible to boot with Generic Serial Flash Interface IP. I tested it on our customer board.

But it is very slowly.

According User Guide the IP core starts with the slowest baudrate. I guess the standard bootloader boot_loader_cfi.srec does not change baurdrate value.

Is there a bootloader available which changes this value?

Or is the source code of the booloader available?

Thanks,

Guenter

[JohnT_Intel]

Hi,

You will need to modify your bootloader in order to change the baud rate. We do not have bootloader specially for Generic Serial Flash Interface IP.

[guenniause]

Hi,

I implemented the setting of the baudrate-register in the standard-loader and it works.

But now I have a problem writing to flash.

I use the following sequence from the reference design:

void write_memory_3byte(){

   IOWR(INTEL_GENERIC_SERIAL_FLASH_INTERFACE_TOP_0_AVL_CSR_BASE,0x4,0x00000000);

   IOWR(INTEL_GENERIC_SERIAL_FLASH_INTERFACE_TOP_0_AVL_CSR_BASE,0x0,0x00000001);

   IOWR(INTEL_GENERIC_SERIAL_FLASH_INTERFACE_TOP_0_AVL_CSR_BASE,0x6,0x00000502);

   IOWR(INTEL_GENERIC_SERIAL_FLASH_INTERFACE_TOP_0_AVL_MEM_BASE,0x00000000,0xabcd1234);

}

The function works fine until the writing address is lower than 0x200000. If I want write to an address above 0x200000 the controller starts no action on SPI bus.

void write_memory_3byte(){

   IOWR(INTEL_GENERIC_SERIAL_FLASH_INTERFACE_TOP_0_AVL_CSR_BASE,0x4,0x00000000);

   IOWR(INTEL_GENERIC_SERIAL_FLASH_INTERFACE_TOP_0_AVL_CSR_BASE,0x0,0x00000001);

   IOWR(INTEL_GENERIC_SERIAL_FLASH_INTERFACE_TOP_0_AVL_CSR_BASE,0x6,0x00000502);

   IOWR(INTEL_GENERIC_SERIAL_FLASH_INTERFACE_TOP_0_AVL_MEM_BASE,0x00200000,0xabcd1234);

}

And after a write above 0x200000, there is no furhter access to SPI bus (for example erase) possible.

The problem cannot not be caused by the flash. Because there is no activity on the SPI bus. The flash is configured with 64Mb.

I lood forward to helpful information.

Thanks,

Guenter

[JohnT_Intel]

Hi,

May I know what is the device density set in your IP? Do you set it correctly? Could you screenshot your Platform Designer?

[guenniause]

Hi,

the density of the flash is set to 64Mb (see screenshot).

So the address 0x200000 should be within the size of the flash.

Thanks,

Guenter

[JohnT_Intel]

Hi,

Thanks for providing the information. You shouldn't be able to access more than 0x200000 as this is over 64Mb addressing. The addressing you used is for 32bit data while the one that shown in Platform Designer is for 8bit data addressing.

[guenniause]

Hi,

thats a important hint. The IOWR instruction works with 32bit addressing.

That will be my problem.

Thanks,

Guenter.

[JohnT_Intel]

Hi,

Are you looking into 8bit data addressing only? Can make your design to work with 32bit data addressing?