System Console & master_write_32 — can't do this while target is running?

[Altera_Forum]

I had a simple controller written in Verilog that was configuring Altera's TSE MAC. Up to this point, it was fairly simple. However, what I wanted to do next is to set a lot of Marvel PHY's settings as well as keep monitoring both PHY and MAC for statistics and errors, etc. Doing that in HW seems like an overkill, so I have decided to incorporate a Nios CPU. But before going ahead and implementing the component in software, I wanted to quickly prototype the idea using System Console. Anyhow, here is my QSys base system: 

 http://i.stack.imgur.com/Su6lY.png   The MAC instance is called tse_mac and the idea is to configure it by reading/writing to control_port through CPU's data_master.  After getting the system up and running, I've connected to it using System Console. I assume it generally works because it is able to get master service path:  % get_service_paths master {/devices/EP2AGX260@1#7-1/(link)/JTAG/(70:34 v3# 0)/nios2_0}   It also opens fine. However, it fails right away when trying to write 32-bit value:  % get_service_paths master {/devices/EP2AGX260@1#7-1/(link)/JTAG/(70:34 v3# 0)/nios2_0} % open_service master "/devices/EP2AGX260@1#7-1/(link)/JTAG/(70:34 v3# 0)/nios2_0" % master_write_32 "/devices/EP2AGX260@1#7-1/(link)/JTAG/(70:34 v3# 0)/nios2_0" 0x400 0x00000000; error: com.altera.systemconsole.internal.plugin.jtag.oci.Nios2DebugException: Can't do this while target is running while executing "master_write_32 {/devices/EP2AGX260@1#7-1/(link)/JTAG/(70:34 v3# 0)/nios2_0} {0x400} {0x00000000}" while executing "master_write_32 "/devices/EP2AGX260@1#7-1/(link)/JTAG/(70:34 v3# 0)/nios2_0" 0x400 0x00000000" %   I have never used System Console before and could not find anything related on the Internet or in the manual. So the question is — what wrongdoing am I committing? Any help solving the problem is appreciated.  (I've also posted this question on SO, here (http://stackoverflow.com/questions/11601699/system-console-over-jtag-fails-to-execute-master-write-32-cant-do-this-while)).  Thank you!

[Altera_Forum]

--- Quote Start ---  ... Any help solving the problem is appreciated....  Thank you!  --- Quote End ---    I guess you'll have to halt the processor in some way, but I don't know how to do that either. A simple way that fits you needs of configuring the MAC + PHY is to add a "JTAG to Avalon Master Bridge" component. It will also show up in the system console like the processor and you can start writing to/reading from your system without halting anything.  Please find below a complete walkthrough:  set path 0]Be sure you'll catch the JTAG Bridge and not the NIOS. Maybe you'll have to insert a 1 instead of a 0. If you want to be sure, remove the NIOS completely :D.  open_service master $pathThis will link the System Console to your master. You could perform  is_service_open master $pathto see wether it worked (=1) or not (=0).  Now you're ready to go with  master_write_32 $path 0x12345678 0xdeadbeefand  master_read_32 $path 0x12345678 1Hope that helped :)

[Altera_Forum]

The other option, if you do not want to stop the CPU, is to put the jtag to avalon master bridge. 

You can find it in bridge section of the component library list.

[Altera_Forum]

--- Quote Start ---  The other option, if you do not want to stop the CPU, is to put the jtag to avalon master bridge. You can find it in bridge section of the component library list.  --- Quote End ---    Thanks for the followup. Yeah it does make sense. One thing I could not comprehend from the error text of the exception is that you have to stop/pause the Nios CPU in order to do what I wanted. Having Jtag to Avalon Master bridge solves the problem, thanks.

[Altera_Forum]

--- Quote Start ---  The other option, if you do not want to stop the CPU, is to put the jtag to avalon master bridge. You can find it in bridge section of the component library list.  --- Quote End ---    :confused:  That's exactly what I said one post earlier...    --- Quote Start ---  A simple way that fits you needs of configuring the MAC + PHY is to add a "JTAG to Avalon Master Bridge" component.  --- Quote End ---  

[Altera_Forum]

--- Quote Start ---  :confused:  That's exactly what I said one post earlier...  --- Quote End ---    Sorry, I should have quoted both of you guys. You both were very helpful, and each gets a hug!

[Altera_Forum]

I think the Jtag Avalon Master component is somewhat faster than the Nios II OCI, but of course it uses more logic. 

 If you want to use the Nios II OCI then the commands you need are [processor_stop <path>] before the memory accesses and [processor_start <path>] afterwards.  Which version of SystemConsole are you using? Version 12.0 and later should stop the processor for you automatically while it does the write, but only if you used claim_service to open it (check the docs for claim_service).