02-14-2012 02:35 PM
Hello.I'm trying to use SDRAM controller with DE2-70 board (SDRAM chip is IS42S16160B): Bits: 16 CS: 1 Banks: 4 Row/Col:13/9 Timing settings from datasheet: http://i43.tinypic.com/2rdup3a.png The QSys system: Nios2 core with SDRAM controller and jtag-uart core. Clock frequency is 143MHz (the source is 50MHz, multiplied in pll), memory clock is -3ns shifted. The problem is that it fails to download simple application (hello world):
Using cable "USB-Blaster ", device 1, instance 0x00 Pausing target processor: not responding. Resetting and trying again: FAILED Leaving target processor paused1. I've checked pins assignments carefully, it is OK. 2. It works if i use onchip RAM instead of external. 3. It works WITHOUT Nios2 core (used it with VIP video frame buffer). 4. Reset pin is assigned to VCC, but i've tried to use jtag reset source, it does not seem to work. Found out many ppl faced the same problem, but unfortunately no solution fits my case.
02-14-2012 05:11 PM
I don't think the JTAG debug/uart can run that fast.You might need to feed a slower clock into the debug module so that it is accesses through a clock crossing bridge. There may also be other timing issues - running at 150MHz needs the timinga analysis be done correctly.