Nios® V/II Embedded Design Suite (EDS)
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Trouble with NIOSII hardware development tutorial

Altera_Forum
Honored Contributor II
‎07-15-2010 02:23 AM
927 Views

I have a problem with the timing requirements. I keep on getting a negative value for the worst-case removal slack. 

I've changed the period setting from 20 to 200000 in 

nanoseconds of the oscillator driving the clock pin,since the clock frequency is 50MHz. What could be the problem? 

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Altera_Forum
Honored Contributor II
‎01-15-2012 07:12 PM
214 Views

Hi, 

I am also having this issue. Has this been rectified? Any suggestions would help :) 

 

Thanks, 

Tiff
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