Unpopulated JTAG header on DE1-SoC

[Altera_Forum]

I can't afford the Altera tools licence so can't debug HPS code over JTAG/Blaster as that isn't afailable with the free toolset. 

 If I solder in a 10 pin header could I then use JTAG & a 3rd party debugger on the HPS side? (I realise teh warranty would probably be void.) If not is there any way to get this functionality?

[Altera_Forum]

I see from the schematic this header has a USB_DISABLE_n signal on pin 2 pulled up to VCC. 

 If I pull this down to ground will this disable the Blaster and take it out of the JTAG chain?

[Altera_Forum]

...Anyone?

[Altera_Forum]

I am looking at options for 3rd party debugger as well. Can you share if you manage to find one that works?

[Altera_Forum]

I'm back on this project now. Can anyone at Terasic provide any information about this JTAG header on the DE1-SoC?

[Altera_Forum]

According to the schematic, it's pretty clear that the intended function of the JTAG header J5 is to automatically tri-state the MAX V pins driving the JTAG chain when connecting an Altera USB adapter (or any adapter with the same pinning). Hopefully this function is supported by the actual MAX V configuration. I would give it a try.  

 You can check the tri-state function before soldering a connector.