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Using IOWR IOED on Cyclone 5 SoC with HPS

Altera_Forum
Honored Contributor II
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Hi, 

 

I have the standard ALTERA timer_core element in (Cyclone 5 SoC with HPS) FPGA. I try to access its registers using: 

# define IOWR(offset, x, data) (*((volatile UINT32*)(offset)) = data) // WR access 

# define IORD(offset, x) (*(volatile UINT32*)(offset)) // RD access 

 

However, I get exception. 

 

Using the same macros for HPS peripherals is fine, no problem... 

 

I wonder, what's wrong? What should I use instead? 

 

Thanks! 

Ran
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Altera_Forum
Honored Contributor II
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You need to add the base address of the peripheral. The reason this works for HPS is that the base offset is fixed and defined starting at 0 rather than the beginning of the device's register space.  

 

All of the standard Altera cores will have code generated for them in the BSP. You should use that rather than writing it yourself.
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