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Weird DDR2 message "...also drives out to other destinations than buffer".

Altera_Forum
Honored Contributor II
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Hi, I've been banging my head against the wall for 2 days now trying to figure this one out. Here is the error that I get: 

 

Error: Illegal connection found on I/O input buffer primitive MEMORY:inst6|mem_if_ddr2_emif_0:the_mem_if_ddr2_emif_0|mem_if_ddr2_emif_0_p0:p0|mem_if_ddr2_emif_0_p0_controller_phy:controller_phy_inst|mem_if_ddr2_emif_0_p0_memphy_top:memphy_top_inst|mem_if_ddr2_emif_0_p0_memphy:umemphy|mem_if_ddr2_emif_0_p0_new_io_pads:uio_pads|mem_if_ddr2_emif_0_p0_altdqdqs:dq_ddio.ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiii:altdq_dqs2_inst|strobe_in. Source IO MEMORY:inst6|mem_if_ddr2_emif_0:the_mem_if_ddr2_emif_0|mem_if_ddr2_emif_0_p0:p0|mem_if_ddr2_emif_0_p0_controller_phy:controller_phy_inst|mem_if_ddr2_emif_0_p0_memphy_top:memphy_top_inst|mem_if_ddr2_emif_0_p0_memphy:umemphy|mem_if_ddr2_emif_0_p0_new_io_pads:uio_pads|mem_if_ddr2_emif_0_p0_altdqdqs:dq_ddio.ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiii:altdq_dqs2_inst|obuf_os_0 also drives out to other destination than the buffer. MEMORY.v is my top block, so I've changed all the input clk; declarations to inout clk; to make them bi-directional but that still hasn't worked. Does anyone have any ideas? 

 

Thanks
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Altera_Forum
Honored Contributor II
362 Views

i was doing DDR3 but ended up with the same error message. have you figured this out yet?:confused:

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Altera_Forum
Honored Contributor II
362 Views

fwei, make sure the ddr3 clk signals are defined as inout, not output.

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Altera_Forum
Honored Contributor II
362 Views

that also happens when you did not connect some pins to the Qsys object.... check if they all are connected.

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