Write the project in EPCS?

[Altera_Forum]

I have the following problem. I want to write the project in EPCS. I use the utility mk_target_board. Further I start Quartus 5.0 full SP1. Then I set the device. Then I start SOPC Builder. I add EPCS Serial Flash Programmer, etc. All according to the document ug_nios2_flash_programmer.pdf. Further I spend generation of system. I pass in Quartus. Then I update a symbol. I set pins and start Compiler. Analysis and Synthesys come to the end successfully, and at a stage fitter arises two mistakes: 

Error: Can't place node and quot; my: inst |epcs_controller: the_epcs_controller | tornado_epcs_controller_atom: the_tornado_epcs_controller_atom|data0out " of type ASMI Block  And Error: Can't fit design in device. Help me to find a mistake! How it can be made?(I use Nios 5.0)

[Altera_Forum]

What came out? Could you solve the problem? 

 I have a similar problem, since I use Quartus II 6.1, a Cyclone II FPGA and Nios II. With the SOPC builder I included an Epcs Serial Flash Controller and I want to use the Serial Flash Loader, too.   When I add the serial flash loader Megafunction in the Quartus II project, what should I do with the nOE_IN pin??? In the document 'Using the Serial FlashLoader With the Quartus II Software' there is a good explanation on how to add the Megafunction to the project, but how to go on? The explanation is  ---------------- Control signal to enable the SFL Megafunction. A low signal enables the Megafunction. SFL tri-states ASMI interface when it is disabled. ---------------- Can I put the the pin low the whole time? But 'The SFL image will be replaced with the new design' after finishing the configuration of the FPGA, right? Will it work then?  To try something else I deleted this serial flash loader symbol from my project and used the serial flash loader as user_defined_interface in the SOPC builder. Generation in SOPC builder worked, Analysis and Synthesis in Quartus II was no problem, but after starting the fitter, the following error occurs: ---------------- Error: Can't place node "Graphik_sopcb:inst5|user_defined_interface_0:the_user_defined_interface_0|s erial_flash_loader:wrapper|altserial_flash_loader:altserial_flash_loader_componen t|data0out_int" of type ASMI block ----------------  Is the Serial Flash Loader already included with using the Epcs Serial Flash Controller? I would like to use the JTAG to program the EPCS configuration device in AS mode via the FPGA using the serial flash loader, but I can't find much information about that.  Any help would be nice, thanks in advance!

[Altera_Forum]

two comments: 

1. the serial flash interface changed from Quartus II 5.0 to 5.1 (and stays the same til now 6.1) you should use a newer version of Quartus 2. now EPCS_controller is the default interface (no need for anything else) to the serial configuration flash, with it it is possible to: - program the hardware and software into EPCS flash from JTAG (from the Nios IDE or using command line tools) - program the EPCS flash from software running on the Nios, there are drivers included in the SOPC component  The Epcs controller is constructed from a small boot ROM and a SPI interface to the serial flash. A good start point for flashing EPCS is the Nios IDE, you can later modify the flashing script created by the ide to learn more about command line flashing tools.  There are some problems with the flashing interface on the 6.1 version of the ide, check some older posts about workarounds (they involve changing the board description name).  IzI

[Altera_Forum]

--- Quote Start ---  originally posted by iztok.jeras@Jan 22 2007, 12:44 PM two comments: 1. the serial flash interface changed from quartus ii 5.0 to 5.1 (and stays the same til now 6.1) you should use a newer version of quartus 2. now epcs_controller is the default interface (no need for anything else) to the serial configuration flash, with it it is possible to: - program the hardware and software into epcs flash from jtag (from the nios ide or using command line tools) - program the epcs flash from software running on the nios, there are drivers included in the sopc component  the epcs controller is constructed from a small boot rom and a spi interface to the serial flash. a good start point for flashing epcs is the nios ide, you can later modify the flashing script created by the ide to learn more about command line flashing tools.  there are some problems with the flashing interface on the 6.1 version of the ide, check some older posts about workarounds (they involve changing the board description name).  izi <div align='right'><{post_snapback}> (index.php?act=findpost&pid=20761)  --- quote end ---    --- Quote End ---    Ok, so if I understood it right, I can totally forget about this serial flash loader (SFL) and only need the Epcs Serial Flash Controller. Then I understand why I found so little documentation about that.   I just thought, I have to use it when I want to have only one 10Pin Connector for JTAG-Debugging and Configuration according to that document: http://www.altera.com/literature/an/an370.pdf (http://www.altera.com/literature/an/an370.pdf), which tells: --------------- Conventional (Active Serial Programming): Advantage: Simple and fast  Disadvantage: Requires separate programming interface to configure FPGAs and program serial configuration devices.  SFL solution (JTAG Programming): Advantage: Able to configure the FPGA and program serial configuration devices using the same JTAG interface Disadvantage: Slow because the SFL solution needs to configure the FPGA before programming serial configuration devices. ---------------  This document was updated July 2006, but I had no idea how old it was and how uptodate the content is.  Thank you very much!!!

[Altera_Forum]

Yes, EPCS controller is enough for all flash programming, you can even program the parallel flash using JTAG, the only problem is not speed but programing failures. With a Linux image of the size of 2MB I get a 25% probability of a programming failure and I have to restart the script. 

 If you are planing to have a processor without a JTAG interface, for higher performance in the final design, than you have to master programming scripts, so you can (in a single script): 1. load the processor with JTAG into the FPGA 2. flash the EPCS with the final hardware and software 3. load the final hardware into the FPGA 4. wait for the software to boot, (no need for power unplagging)  IzI