elf_2_flash command and Cyclone IV Transciever Starter Kit

[Altera_Forum]

This elf_2_flash command  

 elf2flash --base=0x08000000 --end=0x08FFFFFF --reset=0x08800000 --input=<yourfile>_sw.elf --output=<yourfile>_sw.flash --boot=$SOPC_KIT_NIOS2/components/altera_nios2/boot_loader_sources/boot_loader_cfi.sre  Do I assume that the FLASH starts at 0x08000000 and ends at 0x8ffffff and the reset vector is at 0x08000000 + 0x00800000 the offset into the FLASH  to the user code. Does that mean I need to provide a .elf with a start at 0x08800000 ?  My SSRAM is at 0x00000000 where the NIOS II code should end up after the boot loader copied it from FLASH .. I seem to get an error  if I use the actual .elf indicating the base address and the address information in the .elf are not compatible .  Also the Cyclone IV GX Transciever card has Intel JS28F128P33BF FLASH ... I have a NIOS II program running out of SSRAM that dump the SSRAM contents  but when I attempt to dump the the FLASH contents I either get a constant of 0xffffffff. I checked the FLGA load and the CSn is low and the OEn is low and  the address increments I believe every 800 nS and I see read data rerturned. Trying the same thing from NIOS doesn't yield results.  Is there any example out there of the design and polarities and timing setup for the Cyclong IV GX Transciever Card. I can't use the BTS design as a reference since it won't display in Quartus as it was developed with an earlier toolset.  Thnaks, Bob

[Altera_Forum]

I now have the FLASH Tri-State generic controller and Tri-State pin sharing working and can read the various regions of the FLASH via NIOS II .  

 I am able to run the elf2flash command with the --boot parameter. The command I have is below.  elf2flash --base=0x01000000 --end=0x01ffffff --reset=0x01800000 --input=cyclone_sw_flash.elf --output=nios_flash_sw.flash --boot=boot_loader_cfi.srec  And I get a warning that the start address in the .elf is not the same as the reset address, but the output file is generated and reviewing it indicates the  boot_loader_cfi.srec file is at the start of the file. Is the warning expected or do I need to dig into the .elf file to figure out how to avoid the warning.  I can commit the output file to FLASH using the undate portal and dump the user space of the FLASH , indicating the nios_flas_sw.flash file was programmed at offset 0x00800000 in the FLASH.  The problem is that I then think I need to go back to the FPGA design and alter the NIOS II reset vector to point to 0x01800000, the start of the user software space where the start of the boot loader resides. When I do that and then run sof2flash command on the .sof to generate a *_hw.flash file and commit it to FLASH using the update portal the FPGA loads from FLASH but the NIOS II code doesn't appear to run.   Am I missing some step ?  The alternative to moving the reset vector from SSRAM to FLASH would be to swap the mapping of the FLASH and the SSRAM. I have not tried that .