jtag_uart isn't simulated by ModelSim.

[Altera_Forum]

I want to simulate my application from Nios II SBT. I've done successful an example from AN351 and try to repeat it with my Development Kit (Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition) using Standard design example and "Hello world" application. But I got result - all components are simulated (Nios II, DDR e.t.c) but jtag_uart module keeps silence and "Hello world" isn't appeared. 

I use Standard from a disc from of board and got this result. I downloaded updates "Nios II Embedded Evaluation Kit v8.0" and tried to simulate, but got the same result. But it's interesting: Simulation was successful when I used design examples from Nios II SBT from folder \nios2eds\examples (niosII_cycloneII_2c35 and niosII_stratixII_2s60).  I did't a find solution here (or may be didn't see). May be somebody knows how solve this problem?

[Altera_Forum]

Hi: 

I have the same problem with neek and modelsim simulations.   NO SOLUTIONS FOR US UNTIL NOW.

[Altera_Forum]

Does anybody know how to solve this problem? Or nobody has met it?

[Altera_Forum]

can you write down the steps from beginning until the simulation start?  

Are you run this from Nios2 SBT GUI or Nios2-IDE or from command line?

[Altera_Forum]

For simulation my system I use an351-Simulating Nios II Embedded Processor Design step=-by-step. I've tried to run from SBT GUI and Command line, but have no success( What about you? Was it successful?

[Altera_Forum]

I'm having the same problem...silent jtag_uart... 

  win7+quartus10.0sp1+modelsim6.6c

[Altera_Forum]

...I just ran the simulation for longer...2000us and finally saw jtag output

[Altera_Forum]

Thanks for your advice! I'll try it and will write results.

[Altera_Forum]

Attempt was unsuccessful. I ran the simulation for 5000us, but didn't see jtag output (during all time jtag wasn't changing the state) 

to benner4520 What project and design did you use?   Before I simulated my component in previos design (Cyclone II 2c35 from nios II IDE examples folder)

[Altera_Forum]

I believe I had made a project from scratch and included only the Nios II, SDRAM controller (will external PLL), the jtag_uart, and maybe some PIOs and the RS232 controller. Make sure to check all boxes for simulation in the SOPC builer.  

 Does your Nios IDE map your streams to the jtag when using printf for char output or are you trying something different.   Do you see other signals changing in the system?

[Altera_Forum]

Which components has options "simulation"? I saw only in pio-component. 

I've tried to create a new system for Cyclone III with NiosII, SDRAM controller (DDR SDRAM High-Perfomance controller), clock-briges and my component (mac). I've attached a structure of my SOPC-project. Clocks are used the same, like an original standart NEEK design. But this attempt was unseccessful too ( Is it critical to use an internal clock for SDRAM-controller? Because DDR Sdram Controller MegaCore uses pll clock in CycloneII_NiosII design from standart Nios II examples Stdin,stdout uses jtag_uart. Therefore I suppose printf should use jtag_uart too.

[Altera_Forum]

It's awful. I had run for 42000us an didn't get results! I suppose, that increasing a time period - it isn't solution. What should I do?

[Altera_Forum]

Hi Shev, 

 Gerally it´s not a problem to use an internal pll. You just have to take care on constraining of your Pins and on the phase-shift for the external clock!

[Altera_Forum]

Hi, JacoL 

Do you think, that pll is a root of problems? Why?

[Altera_Forum]

Hi again, 

 what I meant is just concerning the SDRAM. If you generate the Clock for the SDRAM in the FPGA via the PLL you have to create two clocks. The internal Clock for the CPU and the SDRAM controller is 100MHz for example. The clock two the SDRAm is 100MHz, too but has a phaseshift to compensate the runtime in the FPGA (at 100MHz roundabout -1ns to -2ns). You can get the right shift from the TimeQuest analyzer. I would try something different with JTAG. Try to decouple the JTAG UART from the clock-crossing bridge and couple it directly to the cpu. Let it run with pll_c0 Clock. Maybe this helps you out.

[Altera_Forum]

I tried to connect directly jtag_uart to cpu without a clock-crossing bridge. But it didn't work either. 

I have a very strange situation - design created for Cyclone III device family in SOPC Builder isn't simulated, but fo Cyclone II is simulated. Why? I don't know. Differences between their structure of design - ddr controller. Now I'm working with the new Quartus project for Cyclone II. Its design is the same like a previous Cyclone III design. It's simulated and jtag_uart works. But I got a new problem - addressing inside my system. I.e. I use cpu, ddr controller, jtag_uart and my component. I create by pll 3 clocks (pll0 - 50Mhz, pll1 - 100Mhz, pll2 - 60Mhz). Cpu uses pll0, jtag_uart and my componet use pll2. There are clock-crossing briges between cpu - ddr controller (ddr_ccb), cpu - jtag_uart and my component (peripheral_ccb) and my_component - ddr_ccb. DDR controller uses the pll0. I use this tangled logic, because the same in preevious Cyclone III design. I generate with SOPC Bulder files for simuation and run in ModelSim the test program (use Nios II Software Builder Tools). This program executes 'malloc', which returns an address. I place data to this address and transmit this address to my component. Than my component tries to read data at this address. But readdata = 32'x. Why? I don't know. May be My component should transform the address. But how should it do?

[Altera_Forum]

Hi again, 

 maybe a screen of this actual sopc builder would be helpfull. Can you post it?

[Altera_Forum]

Of course! )) It's the system for Cyclone II

[Altera_Forum]

I've solved this problem. I chose Skip Calibration (it's approximatly 30ms of the simulation) and used reduced drivers and Small C library. And I got an answer from jtag_uart. 

Long time of the startup code was a root of this problem.