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Hi,
I wrote a very simple Verilog module. This module is an Avalon slave on Nios II. It has 2 registers that can be read and write. I implemented it on a SoPC with where I created: -the Nios II -the jtag -the SDRAM -my Verilog module. I instantied this SoPC on a Top level module also with a PLL to give the right clock to SDRAM. I'm using a DE0 Nano board. Then I wrote also a simple C program:#include "system.h"# include "stdio.h"# include "io.h"
# define REG_BASE (*(volatile unsigned int*) REGISTRI_0_BASE)
int main(){
long int a,b;
a=IORD(REG_BASE, 0);
printf("%ld",a);
IOWR(REG_BASE, 0, 12);
IOWR(REG_BASE, 1, 1);
a=IORD(REG_BASE, 0);
printf("%ld",a);
b=IORD(REG_BASE, 1);
printf("%ld",b);
while(1){
};
}
This program give this output: -1 -1 -1 But i expected 0 12 1 Do you know why? Do you need my verilog code? Thank you
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The verilog would probably help. Thanks!

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