quartus_hps error: send_access_data() error while accessing DP Register

[BuddyZhang]

Hello,

I'm working on the Cyclone V SoC, this may cause by loading a wrong preloader. I have try quartus_hps with argument --boot=18, but it not useful. And there is only one way to boot device from QSPI. Anyone have some suggestion to solve this?

There may be some one with same problem but no answer since 2016.  Re: EDS QSPI programming problem - Intel Community

$ quartus_hps -c 1 -o E -a 0x0 -s 0x40000 -b 18
Info: *******************************************************************
Info: Running Quartus Prime Programmer
Info: Version 20.1.0 Build 711 06/05/2020 SJ Standard Edition
Info: Copyright (C) 2020 Intel Corporation. All rights reserved.
Info: Your use of Intel Corporation's design tools, logic functions
Info: and other software and tools, and any partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Intel Program License
Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
Info: the Intel FPGA IP License Agreement, or other applicable license
Info: agreement, including, without limitation, that your use is for
Info: the sole purpose of programming logic devices manufactured by
Info: Intel and sold by Intel or its authorized distributors. Please
Info: refer to the applicable agreement for further details, at
Info: https://fpgasoftware.intel.com/eula.
Info: Processing started: Mon Nov 20 07:17:48 2023
Info: Command: quartus_hps -c 1 -o E -a 0x0 -s 0x40000 --boot=18
Current hardware is: USB-BlasterII [USB-1]
Successfully change hardware frequency to 16Mhz
Found HPS at device 1
Double check JTAG chain
HPS Device IDCODE: 0x4BA00477
AHB Port is located at port 0
APB Port is located at port 1
Double check device identification ...
Error: send_access_data() error while accessing DP Register
Error: Debug Port Read Buffer reading failure
Error: read_dp_buff() error while accessing AP Register
Error: Fail to READ ACCESS to the Physical Reg
Error: send_access_data() error while accessing DP Register
Error: Encounter JTAG AJI error while reading Control/Status Register
Error: send_access_data() error while accessing AP Register
Error: Fail to READ ACCESS to the Physical Reg
Error: Fail to write to MPU Module Reset Register
Error: Quartus Prime Programmer was unsuccessful. 0 errors, 0 warnings
Error: Peak virtual memory: 4257 megabytes
Error: Processing ended: Mon Nov 20 07:17:51 2023
Error: Elapsed time: 00:00:03
Error: Total CPU time (on all processors): 00:00:00

[aikeu]

Hi BuddyZhang,

May I know iis the board is set to boot from qspi flash?

From your command it looks like you are trying to perform erase on the QSPI flash.

Try to run "qaurtus_hps -c 1 -b 18 -o s" to perform cold reset and read the silicon id of the qspi flash. Would like to know if there is any issue with running this command.

Thanks.

Regards,

Aik Eu

[BuddyZhang]

Hello Aik Eu,

The board do boot from qspi flash and the command out put like following

$ quartus_hps -c 1 -b 18 -o s
Info: *******************************************************************
Info: Running Quartus Prime Programmer
Info: Version 17.1.0 Build 590 10/25/2017 SJ Standard Edition
Info: Copyright (C) 2017 Intel Corporation. All rights reserved.
Info: Your use of Intel Corporation's design tools, logic functions
Info: and other software and tools, and its AMPP partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Intel Program License
Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
Info: the Intel FPGA IP License Agreement, or other applicable license
Info: agreement, including, without limitation, that your use is for
Info: the sole purpose of programming logic devices manufactured by
Info: Intel and sold by Intel or its authorized distributors. Please
Info: refer to the applicable agreement for further details.
Info: Processing started: Wed Nov 22 02:14:25 2023
Info: Command: quartus_hps -c 1 --boot=18 -o s
Current hardware is: USB-Blaster [USB-0]
Found HPS at device 1
Double check JTAG chain
HPS Device IDCODE: 0x4BA00477
AHB Port is located at port 0
APB Port is located at port 1
Double check device identification ...
Error: send_access_data() error while accessing DP Register
Error: Debug Port Read Buffer reading failure
Error: read_dp_buff() error while accessing AP Register
Error: Fail to READ ACCESS to the Physical Reg
Error: send_access_data() error while accessing DP Register
Error: Encounter JTAG AJI error while reading Control/Status Register
Error: send_access_data() error while accessing AP Register
Error: Fail to READ ACCESS to the Physical Reg
Error: Fail to write to MPU Module Reset Register
Error: Quartus Prime Programmer was unsuccessful. 0 errors, 0 warnings
Error: Peak virtual memory: 4285 megabytes
Error: Processing ended: Wed Nov 22 02:14:27 2023
Error: Elapsed time: 00:00:02
Error: Total CPU time (on all processors): 00:00:00

Regards
BuddyZhang

[aikeu]

BuddyZhang,

As I understand that command will not give errors as shown as I never have this issue before regardless of the board has or not been programmed with any relevant or unrelevant content.

Would like to know the physical configuration on the board has been set correctly(referring to building bootloader for Cyclone V to boot from QSPI):

Set BSEL jumpers to boot from 3.3V QSPI device:

BSEL2=1 (left)

BSEL1=1 (left)

BSEL0=1 (left)

Can work with the prebuilt images and perform the qspi flashing steps for the board instead of building the required files.

Try to use later version of quartus programming tools if there is any problem.

Another suggestions is to try with the GUI instead of running the command in terminal.

Link for building bootloader for Cyclone V to boot from QSPI:

https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderCycloneVAndArria10#Cyclone_V_SoC_45_Boot_from_QSPI

Link for using pre-built GSRD:

https://releases.rocketboards.org/2022.11/gsrd/c5_gsrd/

Can feedback to me if there is any problem when runnning the qpsi flash commands from the Cyclone V qpsi boot document.

Thanks.

Regards,

Aik Eu

[BuddyZhang · Accepted solution]

Aik Eu,

I am sure it not cause by hardwar issue.
And finally there is a solution, reset flash while hps boot up then enable and write it
https://forum.rocketboards.org/t/qspi-flash-programming/971

[aikeu]

Hi BuddyZhang,

Thanks for the info.

Hmm... anyway I do not understand that specific kind of handling to this problem.

Is the dev kit you are using a custom board or a development kit?

Plus when manually reset the flash. You just need to perform the reset using the reset button on the board or using an additional added circuit to it?

Thanks.

Regards,

Aik Eu

[BuddyZhang]

Hello Aik Eu,

Its a customer board and use additional circuit.

Regards
BuddyZhang

[aikeu]

Hi BuddyZhang,

Thanks for the info. I will close this threa for now.

Thanks.

Regards,

Aik Eu