Nios® V/II Embedded Design Suite (EDS)
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the line size of instruction cache of NiosII?

Altera_Forum
Honored Contributor II
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is it 32bytes? thanks!

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Altera_Forum
Honored Contributor II
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Yes. 

 

From the Nios II Processor Reference Handbook pg 15-5: 

<div class='quotetop'>QUOTE </div> 

--- Quote Start ---  

Instruction Cache 

The instruction cache memory has the following characteristics: 

* Direct-mapped cache implementation 

* Critical word first 

* 32 bytes (8 words) per cache line[/b] 

--- Quote End ---  

 

Dennis Scott 

Microtronix Datacom Ltd.
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