1185GRE i7 Cache Allocation Technology (CAT) Config Problem

[polarursus]

Dear Community,

I have multiple systems with Core i7 1185GRE processors on UP Xtreme i11 Series boards, I'm using them for realtime applications, and I have to do optimizations now to go further. A cyclic task jitter is higher than expected and high peaks are happening randomly. I'm using Ubuntu 24.04 / 6.8 realtime kernel currently, TCC and all related parameters set up correctly in the BIOS, kernel parameters also set up correctly. The next thing would be to separate allocate dedicated LLC cache ways for realtime cores.

This guide was really helpful, I followed it thorughout the setup. The documentation is implying that I should be able to customize L3 / LLC cache allocation. But in reality I couldn't find make it work using documentations. The standard tool would be RDT / pqos tools, but pqos only lists L2 level cache, it says that L3 is not settable, it does not list them. I also tried to use msr with no luck, the corresponding addresses couldn't be set. 

I understood from this documentation, that on some of the CPU's this is non-architectural, so as of my understanding, standard tools couldn't be used there, so I tried to install TCC Tools 

This article is showing the result of setting LLC cache with this CPU family succesfully, they were using i5 version of this processor, os I suppose it should be done with i7 with no problems.

I tried to use ECI tools, used the (currently) latest v3.3 to generate currently available Ubuntu 22.04 and 24.04 images, tried to install TCC tools using this guide, but I the verification step fails, 

sudo /usr/share/tcc_tools/scripts/setup_ssram/tcc_setup_ssram.sh enable --verify

I'm using UEFI BIOS, at boot time there is an error "No SSRAM Region found!" and "Start RTCM hypervisor runtime driver failed."

I checked the BIOS settings many times very carefully, but I do not have option in the BIOS called Software-SRAM (SSRAM) or Data Streams Optimizer (DSO).

I got stuck, if anybody has some thoughts or experiences with this, any help would be well appreciated.

Many thanks!

[NormanS_Intel]

Hello polarursus,

Thank you for posting in the community!

To ensure you receive the most specialized assistance, we have a dedicated forum that addresses these specific concerns. Therefore, I will be moving this discussion to our Embedded Forum. This will allow our knowledgeable community and experts to provide you with timely and accurate solutions.

Best regards,

Norman S.

Intel Customer Support Engineer

[CarlosAM_INTEL]

Hello, @polarursus:

Thank you for contacting Intel Embedded Community.

We would like to help you but we do not have the information to help you with your request related to the cited third-party motherboard.

Due to this, you should address as a reference your consultations related to the cited third-party motherboard by filling out the form or using any of the channels mentioned on the following website:

 https://up-board.org/contact-us/

Best regards,

@CarlosAM_INTEL.

[Diego_INTEL]

Hello @polarursus,

I was checking this forum, besides what my co-worker mentioned, I would like to add:

Since TCC tools are not actively supported, you may check the following package in Github:

https://github.com/intel/intel-cmt-cat

And document  #786715 - Intel® Time Coordinated Computing (TCC) User Guide.

You can check section "5.1.2.2.1 Example L3 cache partitioning for an 11th Gen Intel® Core™ Processor i7-1185GRE".

You will need a Premier account to get access to this document.

I hope this may be of help.

Best regards,

@Diego_INTEL