AGFB014 FPGA F-tile PCIE Hard IP in 4x4 mode

[Zefu]

Hi,

We are trying to use the AGFB014 FPGA F-tile PCIE hard IP as a PCIE switch, we want to configure the single F-tile in the FPGA as 4 PCIe x4 IPs and use one of them as upstream port, but the other 3 as downstream ports. However, in the IP configuration, there are only two options available, it is either configure all x4 ports to be Downstream or Upstream ports. 

We are wondering if this is a hardware limitation or is there away to configure the IP differently.

thanks a lot

Zefu

[wchiah · Accepted solution]

Hi,

The AGFB014 FPGA F-tile PCIE hard IP is designed with certain configuration options, and the limitation you mentioned is likely a hardware limitation of the IP. Unfortunately, it seems that you cannot individually configure each x4 port to be either upstream or downstream within a single F-tile using the given IP.

To achieve the specific configuration you mentioned, with one upstream port and three downstream ports, you may need to explore alternative solutions. One possible approach could be to use multiple F-tiles and configure each F-tile with a different PCIe configuration. This would require additional FPGA resources and potentially more complex routing and interconnection between the F-tiles.

Alternatively, you could consider using external PCIe switches or PCIe bridge chips that offer the desired configuration options. These chips are specifically designed for PCIe switching and provide flexible configurations for upstream and downstream ports.

Regards

Wincent_Intel

[wchiah]

Hi,

I wish to follow up with you about this case.

Do you have any further questions on this matter ?

​​​​​​​Else I would like to have your permission to close this forum ticket

Regards,

Wincent_Intel

[Zefu]

Thanks Wincent,

If it is a hardware limitation, we will have to use a larger FPGA e.g. AGF027, with 2x F-tile, and configure one of the F-tile to be 4x4 upstream mode, and the other F-tile to be 4x4 downstream mode.

Do you think this will work?

Zefu

[wchiah]

Hi Zefu,

The detail configuration of upstream and downstream mode you can check
https://www.intel.com/content/www/us/en/products/details/fpga/intellectual-property/interface-protocols/pcie-scalable-switch.html

Theoretically, your idea is workable, but as I check we do not have any documented tested on the same configuration.
If you have the resource, you may try to run it. Please let us know if you found any unusual/error.

Regards,

Wincent_Intel

[wchiah]

Hi,

I wish to follow up with you about this case.

Do you have any further questions on this matter ?

​​​​​​​Else I would like to have your permission to close this forum ticket

Regards,

Wincent_Intel

[wchiah]

Hi

We have not hear from you and this Case is idling. It is not recommended to idle for too long.

Therefore following our support policy, I have to put this case in close status. My apologies if any inconvenience cause

Hence, This thread will be transitioned to community support.

If you have a new question, feel free to open a new thread to get support from Intel experts.

Otherwise, the community users will continue to help you on this thread. Thank you

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Regards,

Wincent_Intel