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ALT_INBUF_DIFF and Pin Planner

Altera_Forum
Honored Contributor II
1,212 Views

I'm new to the Quatus Env and hitting a snag when implementing the ALT_INBUF_DIFF. 

 

Top-level I have a LVDS sync_pulse_p and a sync_pulse_n going to the ALT_INBUF_DIFF primitive.  

 

sync_buffer : alt_inbuf_diff 

generic map  

io_standard => "lvds", 

enable_bus_hold => "off", 

weak_pull_up_resistor => "off" 

port map  

(  

i => sync_pulse_p,  

ibar => sync_pulse_n,  

o => sync_pulse 

); 

 

My issues is associated with the Pin Planner. When I set the sync_pulse_p to LVDS in the I/O Standard, it creates a sync_pulse_p(n) signal. If I remove the sync_pulse_n and add sync_pulse_p(n) to the top-level vhdl, I get an error during complilation. What am I missing?
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5 Replies
Altera_Forum
Honored Contributor II
324 Views

why use the ALT_INBUF_DIFF at all? just port sync_pulse to the top level and give it an LVDS I/O Standard in Pin Planner or Assignment Editor

Altera_Forum
Honored Contributor II
324 Views

Okay, but could you explain how to implement this? 

 

For example: 

top.vhdl will have th signal: 

sync_pulse 

 

Pin Planner will have I/O Standard LVDS for the sync_pulse & sync_pulse(n). 

 

What will the final sync_pulse signal be called in the top vhdl file? 

sync_pulse??
Altera_Forum
Honored Contributor II
324 Views

right, just have sync_pulse ported all the way to the top level. in Pin Planner, once you assign it an LVDS I/O standard, the complimentary (n) pin will be created and automatically assigned to the pair where you assigned the p pin. the rest is done by the tool

Altera_Forum
Honored Contributor II
324 Views

Thanks! It worked.  

 

How should I deal with an output? I was thinking about using the ALT_OUTBUF_DIFF.
Altera_Forum
Honored Contributor II
324 Views

it should work just the same for outputs

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