I'm new to the Quatus Env and hitting a snag when implementing the ALT_INBUF_DIFF.Top-level I have a LVDS sync_pulse_p and a sync_pulse_n going to the ALT_INBUF_DIFF primitive. sync_buffer : alt_inbuf_diff
io_standard => "lvds",
enable_bus_hold => "off",
weak_pull_up_resistor => "off"
i => sync_pulse_p,
ibar => sync_pulse_n,
o => sync_pulse
); My issues is associated with the Pin Planner. When I set the sync_pulse_p to LVDS in the I/O Standard, it creates a sync_pulse_p(n) signal. If I remove the sync_pulse_n and add sync_pulse_p(n) to the top-level vhdl, I get an error during complilation. What am I missing?
Okay, but could you explain how to implement this?For example: top.vhdl will have th signal: sync_pulse Pin Planner will have I/O Standard LVDS for the sync_pulse & sync_pulse(n). What will the final sync_pulse signal be called in the top vhdl file? sync_pulse??
right, just have sync_pulse ported all the way to the top level. in Pin Planner, once you assign it an LVDS I/O standard, the complimentary (n) pin will be created and automatically assigned to the pair where you assigned the p pin. the rest is done by the tool