Hi,
I implemented ALTLVDS_Rx with external PLL (instead of ALTLVDS_Rx with internal PLL) to control PLL settings manually. But problem of word alignment arised, I think. In idle mode only "AA"(hex) bytes are transmitted by LVDS, but processing finite state machine detects another bytes received ("55" Hex).
There is a part of my project about ALTLVDS_Rx and PLL in attachment.
Is it right or need some modifications ?
Data rate: 160 Mbps,
Deserialization factor: 8.
Settings of PLL are:
PLL mode: Source Synchronous
Compensate clock: clock0
Compensated input/output pins: lvds_data_rx, lvds_data_rx
Switchover type: --
Input frequency 0: 20.0 MHz
Nominal PFD frequency: 20.0 MHz
Nominal VCO frequency: 320.0 MHz
VCO phase shift step: 390 ps
Freq min lock: 18.75 MHz
Freq max lock: 40.64 MHz
Bandwidth: 680 kHz to 980 kHz
