ATX PLL error in FIT stage

[lance9]

 L-Tile/H-Tile Transcever ATX PLL Intel Sttratix 10 FPGA IP used by PLL. The configured parameters are as shown in the figure below：

But during the FIT stage there will be an error as shown below：

 My PHY is using L-Tile/H-Tile Transcever Native PHY Intel Stratix 10FPGA IP,set the VCCR_GXB and VCCT_GXB  supply voltage for the transceiver to 1_0V, select GXT for transceiver channel type ,select Basic(Enhanced PCS) for Transceiver configuration rules, and set Data rate to 16000M. Use the default parameters for the rest of the settings. 

[Kshitij_Intel]

Hi,

Can you please try with the latest version and let me know your observations.

Also, try to implement standalone PHY IP with PLL and compile it.

And if issue still persists share your standalone project. I will look into it.

Thank you,

Kshitij Goel

[Kshitij_Intel]

Hi,

As we do not receive any response from you on the previous answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Thank you,

Kshitij Goel