Agilex 5 E-Series Ethernet with 1588 via HPS EMAC

[Nicole04]

Good day,

I would like to use the Hard Processor System (HPS) Ethernet Media Access Controller (EMAC) peripheral (with IEEE 1588) for a Gigabit Ethernet (GbE) port. I found the information for this in the Hard Processor System Technical Reference Manual - Agilex 5 SoCs (814346).

I will use an external PHY and SGMII Interface. I would thus route the signals through the FPGA IOs. Should I use the HSIOs or a Transceiver for the SGMII signals? 

How should the MDIO signals be routed? the PHYs I use allow for up to 16 PHYs to be connected via one MDIO bus. Is it possible to combine a non-HPS and HPS GbE port over the same MDIO bus? The PHYs will have different addresses. How should I then route this bus?

Do I still need to use the Triple-Speed Ethernet IP when I use the EMAC? 

[aikeu]

Hi Nicole04,

Let me check with the team regarding your question.

Thanks.

Regards,

Aik Eu

[aikeu]

Hi Nicole04,

Can check with Figure 51 on the Agilex 5 Technical Reference Manual regarding the possible connections.

Refer to 5.1.3.8. PHY Interface as well.

https://www.intel.com/content/www/us/en/docs/programmable/814346/24-1/hard-processor-system-technical-reference.html

If you are going to use HPS EMAC, there is no need to consider the Triple-SPeed Ethernet IP.

Thanks.

Regards,

Aik Eu

[Nicole04]

Hi Aik Eu,

Thank you for your reply. 

I will then not use the Triple-Speed Ethernet IP for this connection. 

Should I use a transceiver or the HSIOs (with TDS) for the SGMII connection between the PHY chip and the FPGA (EMAC)?

If I have another ethernet connection that has to be connected to the FPGA fabric (via SGMII through a transceiver), which will use the Triple-Speed Ethernet IP, can I use a shared MDIO bus between this connection and the EMAC one? Where will the MDIO signals then be connected?

Thank you for your assistance.

Kind regards,

Nicole

[Jeet14 · Accepted solution]

Hi,

Aik Eu is OOO.

Yes you can use the SGMII and SGMII+ using soft logic with the appropriate general purpose, TDS, or transceiver I/O resources. Reference-https://www.intel.com/content/www/us/en/docs/programmable/814346/24-1/phy-interface-01.html

You can also route the MDIO pin to FPGA and with shared MDIO interface for multiple PHY devices and their configuration and management.

Regards

Tiwari

[Jeet14]

Hi

Let me know if you have any query on this.

Regards

Tiwari

[Jeet14]

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[Nicole04]

Hi,

How will the shared MDIO be set up in the platform manager for the TSE IP?

Is it better to use an MDIO EMAC for the HPS EMAC connected ethernet link?