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Arria 10 HPS EMIF DDR4 failing calibration

David32
New Contributor I
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Hi,

We are using Arria 10 SOC on a custom board.

There is a single interface to DDR4 (component, 2 devices, each 16 bits).

When doing normal EMIF the calibration succeeds and I can access memory through System Console and the JTAG Avalon Master.

After copying all parameters to a EMIF HPS IP within Platform Designer, the calibration fails as indicated by the CAL bit in the DDRCALSTAT register.

I have exported the f2h cold reset request and tied it to the EMIF reset input. This signal is driven high by logic some time after configuration ends.

Any help would be greatly appreciated.

Thanks

David

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symmt_Intel
Employee
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Hi David,


What do you mean by "doing normal EMIF"?

Did you mean that you referred to GHRD or something, copied the EMIF parameters and pasted them for your own project?


If you use different DDR4 memories, you need different calibration parameters for sure.


Best regards,

Sho Yamamoto


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David32
New Contributor I
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Hi Sho

"Normal" means the instantiation of the (non HPS) EMIF IP within Platform Designer, since an IP also exists for instantiating EMIF to HPS.

These tests were on our custom board, where the "normal" or non-HPS EMIF controller seems to work OK with the DDR4, but the HPS EMIF controller fails on calibration.

David

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symmt_Intel
Employee
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Hi David,


So you mean you have done non-HPS EMIF testing with EMIF toolkit mentioned in the links below and found no issues, but only when you used HPS EMIF, the issues occurred?

https://www.intel.com/content/www/us/en/docs/programmable/683192/18-1/hps-memory-debug.html

https://www.intel.com/content/www/us/en/support/programmable/support-resources/support-centers/emif-support.html


Best regards,

Sho Yamamoto




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David32
New Contributor I
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Hi Sho,

 

Yes that is correct.

Two things are working when using a non-HPS EMIF controller:

1. EMIF toolkit. I manage to create eye diagrams, do re-calibration, etc. Everything seems OK (except for running TG - which I think is more a compatibility issue within Intel since it seems that TG is not supported with Arria 10)

2. From within System Console via JTAG master I can read/write the DDR4 successfully.

 

In a different project I use now instantiate a HPS EMIF controller, along with HPS etc.

Here the boot software always reads from the CALSTAT register that calibration is failing.

David

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