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Arria10 FPGA config directly from TFTP

TG_GER
Beginner
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I have an ARRIA10 SoC FPGA,

and the memory card need to supposed to be hardware write-protected. At the end only u-boot is present on the SD card. It should retrieve the FPGA configuration, kernel, etc., via TFTP and boot. Unfortunately, the FPGA configuration is too large for the SDRAM, even with a separated configuration to activate the DDR RAM; the peripheral is also too large.

Can I load the configuration directly from TFTP into the FPGA without first storing it in RAM?

dear,

TG

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aikeu
Employee
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Hi TG_GER,


From my understanding, I see the tftp operation will eventually run the cmd 'fpga load' and is relying on the RAM to load the FPGA design into the FPGA fabric. Example like loading the rbf from sd card to the fabric will use the same 'fpga load' cmd. I think you will require to inrease the physical DDR ram size for your application.


Thank.

Regards,

Aik Eu


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TG_GER
Beginner
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Hi,

Thank you for the prompt response.

The problem is, I am unable to utilize the external DDR RAM (4GB) as it is connected to the FPGA side. While I can configure the RAM with early IO release, the peripheral from the early IO is larger than 256k (SDRAM size). Consequently, I am unable to retrieve it from TFTP to RAM and then transfer it to the FPGA. Saving the configuration part on the hardware protection SD card poses a challenge as I can never perform a config update since the peripheral and core config must be from the same build.

Do you have any other ideas on how to resolve this issue?

Kind regards,

TG

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aikeu
Employee
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Hi TG_GER,


I think you are following the steps for the Arria10 sd card booting:

https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderCycloneVAndArria10#Arria_10_SoC_45_Boot_from_SD_Card

When your uboot boot up, what is the size of the DDR that is showing in the logs?


Thanks.

Regards,

Aik Eu


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TG_GER
Beginner
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Hi Aik Eu,

yes here is a boot from SD-Card with my old bootloader and config files placed at sd card.

image001.png

so i have 2gb of DDR Ram but only after FPGA config. 

dear,

TG

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aikeu
Employee
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Hi TG_GER,


Sorry for the late reply.

From your logs, the socfpga.rbf is configured where the 2gb ram is available for HPS usage. You proceed to load the core.rbf from the sd card to the ram address 0x50000 then with fpga load to configure the core.rbf.

The socfpga.rbf should be the periphery.rbf. Configuration of periphery: this allows HPS DDRAM to be brought up, and must do be done in SPL

The ddr which is used by the HPS is normally determined in Uboot fsbl in the early stage which is in your case is the 2gb ram.

Refer to this building bootloader documentation as reference on seperate configurations:

https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderCycloneVAndArria10#Option_351_45_Separate_Configuration_Files


Thanks.

Regards,

Aik Eu


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TG_GER
Beginner
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Hi Aik Eu,

Thanks for the reply.

Yes, but the goal is not to have a config on the SD card, as this is hardware write-protected and therefore no updates would be possible. Only the bootloader should be there. The rest via TFTP.

However, the peripheral is too large for the SDRAM to load it from the TFTP into the FPGA.

Is there a way to do a full config again later from Linux? Then I could leave the "old" config on the SD card and always reload the current one in the second step.

 

Here at this link:

Booting Altera SoC FPGA from Network using TFTP and NFS | Documentation | RocketBoards.org

this what i want to do.

there is a info with

"2/27/19 update: These procedures have been successfully tested on an Arria 10 board using the Achilles Dev Kit from REFLEX CES. [DN]"

But how does it works without enough RAM?!

 

thank,

TG

 

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aikeu
Employee
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Hi TG_GER,


If I understood correctly, I think the peripherals.rbf should consider the total size of the ram which can be used in your system and it should consider the 4gb external ram in your design as well. I think the HPS EMIF interface will need to consider the 4gb external ram as well. Below is the reference regarding the early IO release.

https://www.intel.com/content/www/us/en/docs/programmable/683437/current/introduction.html#:~:text=1.-,Introduction,Interface%20(EMIF)%20if%20present.

"

Early I/O Release Use Cases

There are a few different reasons why you might choose to enable the Early I/O

Release feature of the Intel Arria 10 SoC FPGA device. The typical reason is to speed

up system boot and configuration time. By gaining early access to a large pool of

system RAM connected the HPS EMIF interface, the boot software can more efficiently

load the bulk of the FPGA configuration image from mass storage. Restricting boot

code to on-chip RAM typically impedes bulk transfers because of the limited code and

buffer space.



Thanks.

Regards,

Aik Eu


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aikeu
Employee
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Hi TG_GER,


I cant be sure that you can consider the 4GB FPGA ram from the start of configuration.

I think you will still need to increase your HPS ram size for your application purpose.


Thanks.

Regards,

Aik Eu


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aikeu
Employee
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Hi TG_GER,


We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


Thanks.

Regards,

Aik Eu


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