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Assistance Needed: Trouble Running Bare-Metal Code on second core Cyclone 5 HPS

ALTERA-INSUPPORT22
New Contributor I
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I am working on intel cyclone 5 hps I have two cores in a processor Core 0 core 1, I want two code to run on two different cores core 0 and core 1 in bare metal .


When I run in jtag mode it works, for jtag i first debug using core 0 where i take core 1 out of reset it, than debug core 1 usign jtag it work


BUT, When i want to run both core usign qspi it only run core 0 not core 1


Here is the step i followed

Firsly, loading preloader
quartus_hps -c 1 -o P preloader-mkpimage.bin

I make an image from bin file of core 0 and place it to qspi

mkimage -A arm -O u-boot -T standalone -C none -a 0x00060000 -e 0 -n "baremetal image" -d core0.bin core0.img

quartus_hps -c 1 -o P -a 0x00060000 core0.img

I make an image from bin file of core 1 and place it to qspi
mkimage -A arm -O u-boot -T standalone -C none -a 0x00100000 -e 0 -n "baremetal image" -d core1.bin core1.img
quartus_hps -c 1 -o P -a 0x00100000 core1.bin


When i restart board only that code work which is in core 0, core 1 code not executing

I am setting cpu1startaddress 100000 apart from that in the code of core 0 also i am using alt_qspi function to to place bin file data in ddr, 

I want to run in smp mode so I also set required aux_control_register smp and fw bit as stated in tech ref manual  


alt_qspi_read((uint32_t *)BL_START/*ddr3 address*/, 0x100000/*qspi address*/, 0x40000);


In linker/scat file core 0 entry point is 0x60000 and

linker/scat file core 1 entry point is 0x100000

 

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ALTERA-INSUPPORT22
New Contributor I
1,243 Views

@ anyone ?

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JingyangTeh
Employee
1,224 Views

Hi


Sorry to inform you that we no longer support SMP programming anymore.

It is possible but however we no longer provide support for this area of expertise.


Regards

Jingyang, Teh


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ALTERA-INSUPPORT22
New Contributor I
1,207 Views

 

@JingyangTeh I want to up the core 1, if not in smp may be in amp but I want core 1 to bring up as it is working fine in case I use it with debugger
Regards

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ALTERA-INSUPPORT22
New Contributor I
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JingyangTeh
Employee
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Hi


There are no official document related to this.

However do give me sometime to gather some information to run an application on separate cores.


Regards

Jingyang, Teh



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ALTERA-INSUPPORT22
New Contributor I
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ALTERA-INSUPPORT22
New Contributor I
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JingyangTeh
Employee
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Hi 


This is what I could gathered.

You would need to bring the core1 up in your main application in core0.

As stated in this document

https://developer.arm.com/documentation/ddi0407/i/clocks--resets--and-power-management/power-management/multiprocessor-bring-up?lang=en


From the Register map you would need to write to the SCU 

https://www.intel.com/content/www/us/en/programmable/hps/cyclone-v/hps.html#sfo1410068407646.html


First set the bits of address 0xFFFEC00C to 0xFFFEC010 with 0. This invalidates all the SCU for all cores.

Then you could set the bits of address 0xFFFEC005 with 0. This enable the SMP mode for all cores.



Could you also share me your current project files that you have done so far?

So that I could test the flow out on my end too.


Regards

Jingyang, Teh



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ALTERA-INSUPPORT22
New Contributor I
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@JingyangTeh 

Please find core0.c core0.scat core1.c core1.scat in the zip file (attached), you can use your Cyclone V board and other settings.


Also, core 0 reset vector table is managed on startup can you please specify how to manage the reset handle / reset vector table  to core 1 so that it jumps to 0x100000

Regards 


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ALTERA-INSUPPORT22
New Contributor I
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@JingyangTeh  ?

 

 

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JingyangTeh
Employee
757 Views

Hi


Sorry I could not managed to bring up the core1 on the cyclone5.

I tried engaging our engineering team but they are busy with other newer product in line and could not work on this issue.

Right now we do not support AMP mode running on our devices.


Regards

Jingyang, Teh


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ALTERA-INSUPPORT22
New Contributor I
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@JingyangTeh  then please provide me with any project similar to my issue, that is handling multiprocessing of dual-core at bare-metal level of any intel soc. I'll manage the configuration according to my board. Waiting for your quick and timely action.
Regards

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JingyangTeh
Employee
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Hi


We do not have any example design for running application on separate core.

However we do got an example design which uses the Nios II processor as a separate core solution.

https://www.rocketboards.org/foswiki/Projects/DeviceWideAMP


Regards

Jingyang, Teh


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JingyangTeh
Employee
549 Views

Hi


Since this thread been resolve, I shall set this thread to close pending. If you still need further assistance, you are welcome to reopen this thread within 20days or open a new thread, some one will be right with you. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


If you happened to close this thread you might receive a survey. If you think you would rank your support experience less than 4 out of 10, please allow me to correct it before closing or if the problem can’t be corrected, please let me know the cause so that I may improve your future service experience.


Regards

Jingyang, Teh


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