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Can I apply REFCLK to the FPGA while powered down?

fgfasfafgfdhagdszfea
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I have a situation where it is possible that the PCIe system could be powered-up while the board with the FPGA could be completely powered-down. The board with the FPGA doesn't share any of the power rails from the PCIe system other than GND.

This means that it is likely that the REFCLK would be applied to the FPGA when it is completely unpowered. I'm having trouble looking through the documentation to determine whether this is OK or if I will need to implement some kind of solution. Does anyone have any information? REFLK would be going into a dedicated transceiver REFCLK pin.

Similar to the paragraph above, would there be any problems or damage if the FPGA's PCIe RX pins were driven while unpowered?

Thanks for any help or information about which parameter or datasheet to look at.

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1 Solution
skbeh
Employee
189 Views

Hi

Based on PCIe specification, REFCLK usually comes from rootport CPU via pcie edge connector, users have no control on the CPU side to turn-on/turn-off the REFCLK supply, this is a common scenario, it is okay to continue apply the REFCLK to the FPGA when it is completely unpowered. Similar to the Rx pins, it can be drive while unpowered. 


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7 Replies
skbeh
Employee
190 Views

Hi

Based on PCIe specification, REFCLK usually comes from rootport CPU via pcie edge connector, users have no control on the CPU side to turn-on/turn-off the REFCLK supply, this is a common scenario, it is okay to continue apply the REFCLK to the FPGA when it is completely unpowered. Similar to the Rx pins, it can be drive while unpowered. 


fgfasfafgfdhagdszfea
166 Views

Thanks for that information, this will be very helpful for the design.

 

Is this information documented somewhere, if so, where is it? Or does it just require inside knowledge?

skbeh
Employee
156 Views

Functionally it’s a don’t care – even if the FPGA gets the refclk, the PCIe will eventually give up because either it won’t detect a link partner or not get trained.

I didn't see this information is documented, documentations mostly describe about how the pcie core works, oppose to this un-driven scenario.

 

fgfasfafgfdhagdszfea
146 Views

I'm less worried from a software standpoint, and more worried from a hardware standpoint, whether the absolute maximum voltage or current ratings could be exceeded if the FPGA was driven unpowered. Causing physical damage to the FPGA.

skbeh
Employee
136 Views

All fpga IOs are equipped with internal weak pull-up when they are powered-off, so when the IOs are being driven during powered-off, it will not damage.

fgfasfafgfdhagdszfea
113 Views

I'm reading some more of the documentation and the Core Fabric document links to here for "Transceiver Pin Guidance for Unpowered FPGA"

https://www.intel.com/content/www/us/en/docs/programmable/683725/current/transceiver-pin-guidance-fo... 

 

Does this contradict what you are saying? This document seems to say you can't drive any of the pins when the FPGA is unpowered.

 

Sorry to keep harping on this, but I need to be completely sure the design won't be damaged, so I really want a specific document stating that this is safe. This document seems to say it is NOT safe.

skbeh
Employee
106 Views

I've found this KDB answer for the REFCLK. 

https://www.intel.com/content/www/us/en/support/programmable/articles/000084997.html

"The Arria® 10 device dedicated transceiver REFCLK pins are not subject to the same hot-socketing limitations of the general purpose I/O pins. It is OK to drive the dedicated transceiver REFCLK pins during power-up and power-down sequencing of Arria 10 devices."


However, based on AN692 1.3.2. Transceiver Pin Guidance for Unpowered FPGA

Intel® Cyclone® 10 GX, Intel® Arria® 10, and Intel® Stratix® 10 L-tile and H-tile device transceiver pins do not support ‘Hot-Socketing.’

Fully configure the transceiver block before driving or having any activity on the device transceiver pins.

In the handbook says that do not drive the transceiver and IO pins externally during the power-up and power-down time to avoid excess current.


For PCIe link, the suggestions are:

1) add analog switches to open the PCIe link.

2) another advice would be for you to disable to the PCIe ports on your host first, to ensure that you are not attempting to link train to a card that your system has decided to be fitted but not powered.


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