Can not write or read in SDR SDRAM

[Altera_Forum]

Hi, 

I am using FPGA Stratix II EP2S60F1020C4. This FPGA board has 2 SDRAM ( Micron MT48LC4M32B2 ) configured as 64-bit bus. These two SDRAM have their control signals connected on the same pins of FPGA except for DQ and DQM. Control signals connected on the same pins are :CLK, CKE, CS, SA, BA, RAS, CAS, WE (eg. CS of 2 SDRAM are connected to pin AL6, SA connected to pin AK4,...).  I am trying to write into and read data from SDRAM. I use SDRAM controller core 2000 from Altera. I also write a user program to assert DATA, ADDRESS and COMMANDS to SDRAM controller based on SDRAM controller manual in order to implement SDRAM controller with SDRAM device.  My program is written to do these tasks: Initiate SDRAM, Write a 32 bit data into an address, Read data from the same address, and Check data read with 8 LEDs. I have compiled my program with Quartus II 7.0 and got no errors and no timing warnings.  However, when this program is applied in FPGA, the data read from SDRAM (given by out put of SDRAM controller) is always FFFF (checked by LEDs),although the data at DQ pin of SDRAM (checked by LEDs) is the same as the data I want to write into SDRAM. It seems that the program can not write data into SDRAM,or can not read. I am not sure, because I do not know any other ways to check.  I have tried a lot to figure out why my program does not work properly, but I still can not solve this problem. I am quite new to FPGA as well as SDRAM. My study in university is deal with writing and reading data in SDRAM, therefore; it is very important to me to use SDRAM.  Can any body help me to solve this problem? Thank you very much in advance.   Here is my program and SDRAM controller core manual    https://www.alteraforum.com/forum/attachment.php?attachmentid=1135   https://www.alteraforum.com/forum/attachment.php?attachmentid=1136

[Altera_Forum]

I can confirm, that the WP SDRAM code is basically working. Depending on the FPGA family, constraints may be necessary to enforce e.g. the usage of fast OE registers. But because you are only showing a sub-entety of your code, nobody can check if you interfaced the SDR code correctly. Also, you apparently had to apply some changes to the originally 16-Bit wide code. There are many details, that may have gone wrong adapting the code. 

 I didn't check, if you possibly missed something essential in the RAM handling, because I prefer to see the whole thing, first.  I don't know, if I'll have the time to check the code in detail. But also for others, that can possibly help: Please assemble a minimal test project, including the SDR code and all pin assignments (I guess, you're using an existing Dev. Kit) in a *.qar project archive.  P.S.: In the meantime, you should learn how to use SignalTap II to display the RAM signals. Start with the RAM initialisation, then write, read. Check if all RAM signals are as they should be expected according to the Micron RAM datasheet respectively the controller documentation.

[Altera_Forum]

Thank you very much for your kind answer. 

 I have attached here my project for SDRAM control so that you can check it conveniently. I hope you will help me to point out what is wrong with my project. It is really important for me to get through this problem because it is one part of my master thesis.   By the way, thank you very much for your helpful advice about Signal Tap II. I will try to use it.   Looking forward to your reply.:)    https://www.alteraforum.com/forum/attachment.php?attachmentid=1137