Changing data width in floating point ip vs using fixed point

Altera_Forum · ‎12-11-2010

I am confused in trying to differentiate among the two options:

Changing the default data width(32 bits) in Altera floating point ip cores vs Using fixed point ip. Are these two things not the same? If I can reduce the data width of a Altera floating point ip to something of my choice then will it not be the same and as good as using fixed point arithmetic?

Thanks for any replies.

Altera_Forum · ‎12-11-2010

The FP MegaFunction data width can't be reduced below 32 bit single precision. FP format (it's using a normalized mantissa and an exponent) is basically different from fixed point format.

Altera_Forum · ‎12-11-2010

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The FP MegaFunction data width can't be reduced below 32 bit single precision. FP format (it's using a normalized mantissa and an exponent) is basically different from fixed point format.

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So, if I wanted to use fixed point arithmetic would that mean that I would have to write my own cores for all the arithmetic(+,-,/,*,exp) myself?

Altera_Forum · ‎12-12-2010

I now understand the difference between fixed and floating point well. So to use the fixed point arithmetic with Verilog, is there no library support like in VHDL? Also consider the following:

reg [7:0] a;

reg [7:0] b;

reg [15:0] c;

c<=a*b;

c<=a/b;

c<=a+b;

c<=a-b;

Would the following expressions be valid for +,-,/,* operations in fixed point arithmetic? Thanks for the pointers.