Constraints in SDC file

[Altera_Forum]

Hello,  

 I have been receiving a warning in TimeQuest Analyzer because I am using an output port from one of the logical elements in my design (State Machine) to drive the clock of a shift register. TimeQuest wants me to add a constraint for this output and classify it as a clock. How do I add constraints to lines inside my design that are not explicitly connected to I/O pins on the FPGA. Thanks.

[Altera_Forum]

You can figure it out from the TimeQuest create_generated_clock documentation and from the example at http://www.altera.com/support/examples/timequest/exm-tq-generated-clock.html. 

 Be aware of the cautions at http://www.alteraforum.com/forum/showthread.php?t=2388 if you insist on using logic to drive a clock signal. Maybe you can change your design to a better implementation like a clock enable as discussed in the other thread. If this is for a class assignment, it would be best to learn how to follow the preferred FPGA recommended design practices for clocks.