Converting Oscillator HCSL Output to SSTL_18

[shaneh_fl]

I am designing a PCB with a MAX 10 (10M50DAF256) with DDR2 and the MAX 10 requires a SSTL_18 clock source. I found Renesas AN-891 online and it describes using a HCSL driver, series 0.1uF capacitors and resistor voltage divider network tied to VCC1V8 to convert to SSTL. Has anyone done this in their design? Will it work? I chose the Epson SG3225HBN to use. I really don't have the need or the room for a 1x8 CLK BUFFER IC with a SSTL output. Please advise.

[FvM]

You can select LVDS IO standard to receive HCSL clock at MAX10.

[shaneh_fl]

Thanks for the reply but I do require a differential SSTL_18 100MHz source since I am using DDR2. All assigned pins to Banks 5 and 6 are set to SSTL_18.  Also, VREF to both banks is 900mV. 

[FvM]

Not clear what you want achieve. DDR IP expects that RAM clock is sourced by FPGA not an external oscillator.

[shaneh_fl]

I have the MAX 10 EVAL KIT and it uses a custom programmed Si5338A and one of its outputs is the CLK_DDR3_100 to the FPGA. I bring this into Platform Designer using a Clock Bridge IP and I am able to get the the DDR3 IP up and running with this clock source. So I am just trying to duplicate this with my DDR2 design on a custom PCB.

The CLK_DDR3_100 differential outputs of the Si5338A-CUSTOM are tied to series 0.1uF caps and then are pulled up to VCC1V5 and down to GND with 2Kohm resistors which provide a reference of 750mV. After seeing Renesas AN-891 and knowing the MAX 10 requires at least 500mVpp for SSTL_18, I am assuming that the output of the Si5338A-CUSTOM is HCSL. I think my circuit will satisfy the differential SSTL_18 input requirement for the MAX 10. I am just wondering if anyone has done this with a discrete oscillator that has a HCSL output or can tell that this should work. I guess if it does not work as intended I can use a FPGA generated 100MHz PLL for the DDR2 IP. Thank you for replying to my posts.

[FvM]

Hi,

thanks for referring to MAX10 FPGA Development Kit for clarification. I expect that respective capacitive coupling  will also work for differential SSTL-18 clock input. According to my knowledge, differential clock input uses always the same differential input buffer. Actual common mode range is larger and minimal differential input voltage smaller than SSTL spec suggests. The clock input will most likely work driven by HCSL without capacitive coupling.

On the other hand, I don't see a purpose of having a separate clock source for DDR3 RAM IP. You'll preferably use an internal  PLL source with defined phase relation to other design clock domains.

[FvM]

Hi,
other than assumed above, differential SSTL-18 input buffer seems to work differently from true differential inputs like LVDS. 

There's this comment about differential SSTL-xx and HSTL-xx inputs in the handbook:
"The inputs treat differential inputs as two single-ended inputs and decode only one of them" ( Intel® MAX® 10 General Purpose I/O User Guide 683751 2022.10.31, p 7). 

It's also stated in MAX10 datasheet: "Differential SSTL requires a VREF input."

[FvM]

Hi,
I did a test on an existing board with LVDS input. I switched the IO-standard to differential SSTL-2 class I and supplied a variable VREF voltage. The circuit behaves as if CLK_P input is compared with VREF while CLK_N is ignored. Switching to single-ended SSTL-2 results in identical behaviour, also identical VREF margins. Seems like there's no difference between single-ended and differential SSTL for an input. Respectively required input swing is double the magnitude needed for a true differential input. You also need to care for input bias matching VREF. 

A possible advantage of using differential over single ended SSTL is that charge injection to VREF node is cancelled, presuming there's a second input buffer connected to CLK_N. 

[AqidAyman_Intel]

Thank you Frank for sharing your input.

With that I wish to follow up, is there any other help or support needed for this issue?

[shaneh_fl]

Thanks to all for the inputs for my post. They were very helpful. I am hopeful that my HCSL to SSTL_18 conversion will work. I will find out in a month or two. If the MAX 10 does not like it, I can use a generated 100MHz PLL to source the DDR2 IP which is good insurance.

[AqidAyman_Intel]

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.