I would be trying to use a receive clock provided to the FPGA along with the data as well as a frame valid signal. I am using the IP core and was wondering how do you define the connection in the vhdl file. Looks like the IP only defines 1 side of the input pin, so do I only need to define 1 pin input at the top level as well?
IP snippet
component LVDS_RX is
port(
rx_in : in std_logic_vector(0 downto 0);
rx_inclock : in std_logic;
rx_out : std_logic_vector(7 downto 0);
My top level snippet
entity TopLevel is
port (
nrst : in std_logic; -- active los
clkin : in std_logic;
rx_in_sig : in std_logic;
);
end TopLevel;
Thanks!
