Cyclone 10GX PCI express without clk_user any solution ?

[manu-solystic]

I have a prototype design with a Cyclone 10GX

I want to use the PCI express , but the clk_user is not connected
And if i read the documentation about the PCI express with cyclone 10Gx , this clock seems to be mandatory

But on my design, it's not possible to connect the CLK_USR  (The pin is not accessible)

Does any have a suggested solution, to have a a PCI express working 
With the use of a other clock connected to the FPGA.  with an internal connection.
I have a 100Mhz LVDS clock connected to the Cyclone 10GX, and I have also a 25Mhz HCMOS clock connected to the FPGA

These clock are used in the Cyclone 10GX design

Thanks for any answer 

Regards

Manuel Ribeiro 

[wchiah]

Hi,

I will close this and moving to due to replication

https://community.intel.com/t5/forums/forumtopicpage/board-id/fpga-intellectual-property/message-id/26930#M26930

Let us continue there.

Regards,

Wincent_Intel