Cyclone 10LP PLL Switchover

[Chris_Cres]

I'm trying to implement the switchover functionality of ALTPLL IP on Cyclone 10LP.

The purpose is to be abble to select between 9.2Mhz and 4.6MHz frequency and manage phase **bleep**f as well.

When I clcik the add inclk1 input the Wyzard comes with unable to  generate PLL if the I use these two frequencies....

It seems that the VCO is to high.

Is there any way to use that IP it that king of application and frequency range?

If not is it possible to use simple **bleep** register with timing constrain between internal clock and output genrated signal (used as clock for external device)?

Looking forward to hearing from you back

Best regards

[Ronny_G_Intel]

Hi Chris_Cres,

Thank you for contacting Intel Communities.

I am not knowledgeable about Cyclone 10LP PLL Switchover, but after running a quick search, I believe this issue is not related to Intel® QuickAssist Technology (Intel® QAT). It may be related to the FPGA family of products.

I am routing this post to the FPGA community.

Regards,

Ronny G

[FvM]

Hi,
it's not completely clear what the problem is. Can give an example of actual input and output frequencies that can't be implemented?

Regards
Frank