Cyclone III RAM Question

[Altera_Forum]

Okay, so the Cyclone III RAM has been changed from an M4K block to an M9K block. Why was this change made? Most of the FPGA designers I know are using a lot of distributed RAM, so it is counter-intuitive to me that Altera would choose to go for a larger block size as opposed to a smaller one. I have the impression this makes the architecture less efficient, in cases where I just need some smaller blocks of RAM. 

 any ideas?   GG

[Altera_Forum]

Lots of applications require memory blocks that are over 4Kb, so moving up to 9Kb makes sense. Again, a lot of this is dependent on your application. Since it's a programmable device, Altera needs to design the chips to address the needs of the majority of it's customers. There are bound to be cases where the 9Kb block is not ideal, but there should be more cases where it is ideal.

[Altera_Forum]

The larger block size is not a problem as long as the number of blocks is not decreased. Quartus can pack more than 1 memory function into a block in some cases.

[Altera_Forum]

Larger memories make more efficient the majoraty of the projects, but if you use smal memories, you can set Quartus to divide the memory block, depending on your project and the performance you need you can do this in VHDL or Verilog too, using a personal ofset to do so.