Cyclone Ⅳ PLL Output Clock Frequency not Right

[jiec]

Hi,

I am using the chip EP4CE15M8I7N, andi tried to use PLL in ip-core, but the frequency of the clock output is wrong. The frequency of the input clock is 50MHz, and what the frequency of the output i hope is 5MHz. But the fact is the output frequency is not right.

The clock from osc to supply into the chip is 50MHz which have been verified,  but the frequency of clock output from pll just only range from 30KHz to 50KHz.

In addition, the code i have used in EP4CE10F15 and it's work, the output freency is right. 

So I don't know how to solve this problem, is it some requirement in code or quartus ii when i used this chip EP4CE15M8I7N?

This issue has been troubling me for a long time, please help me, hope some replies, Thank you!

[FvM · Accepted solution]

Hi,
low frequency PLL output is usually indicating missing input clock. I suspect wrong pin assignment or similar.

Regards
Frank

[jiec]

Hi,

Frank

Thanks for your reply, I am trying to solve this problem by your suggestion, and I will reply u again in few days, Thanks again!

Jiec

[jiec]

Hi,

Frank

Thanks again for your reply, I found that our hard design have some problem about power supply of the pin of PLL, we are going to solve it, Thanks!

[jiec]

Hi,Frank

Thanks for your reply, I am trying to solve this problem by your suggestion, and I will reply u again in few days, Thanks again!

Jiec