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DDR Control lines (DQS0T & DM0T) questions on the E144 Cyclone III

Altera_Forum
Honored Contributor II
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Hello. 

 

I am currently trying to make pin assignments from my DDR memory controller instantiated in the SOPC builder but have run into a couple of problems: 

 

1. As I understand it, the manual for external memory interfaces states that the DQS (data strobes) and DM (data masking) pins are equivalent in that both have dedicated pins associated with a specific group of pins (the data I/Os, DQ). 

I have found the DM pin for the top group but there doesn't seem to be one for the bottom group. 

 

What should I do in this case?  

I don't see a need for data masking (though some of my Avalon-MMs might) but surely these pins on the memory need to be driven for it to function at all. 

Would it be acceptable to tie both the DMs together? If I do this how to I prevent the DDR controller from trying to use data masking? 

 

EDIT: I have decided to use a different memory from the same manufacturer but with a x8 organization so I do not need the second data bank and thus the DM, but would still be interested to know for future reference what would be done if this wasn't an option. 

 

2. Not really a problem but I see in the pin list [http://www.altera.com/literature/dp/cyclone3/ep3c16.pdf] that there are two data strobes, DQS0B and DQS0T, with no associated DQ pins. What is the purpose of these pins? 

 

Thanks.
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